Toshiba TLCS-900 manuals
Computer Equipment > Network Card
When we buy new device such as Toshiba TLCS-900 we often through away most of the documentation but the warranty.
Very often issues with Toshiba TLCS-900 begin only after the warranty period ends and you may want to find how to repair it or just do some service work.
Even oftener it is hard to remember what does each function in Network Card Toshiba TLCS-900 is responsible for and what options to choose for expected result.
Fortunately you can find all manuals for Network Card on our side using links below.
751 pages 4.31 Mb
Data Book 32bit Micro controller TLCS-900/H1 series TMP92CZ26AXBG Rev0.2 09/Dec./2005 TENTATIVE 2 Table of Contents TLCS-900/H1 Devices TMP92CZ26A CMOS 32-Bit Micro controllers 4 TMP92CZ26AXBG 1. Outline and Features 9 2. Pin Assignment and Pin Functions 2.1 Pin Assignment Diagram (Top View) TMP92CZ26A10 TMP92CZ26A 92CZ26A-7 Table 2.1.1 Pin number and the name TMP92CZ26A 92CZ26A-8 11 2.2 Pin names and Functions12 TMP92CZ26A 92CZ26A-9 T able 2.2.1 Pin names and functions (2/6) 13 TMP92CZ26A 92CZ26A-10 Table 2.2.1 Pin names and functions (3/6) 14 TMP92CZ26A 92CZ26A-11 Table 2.2.1 Pin names and functions (4/6) 15 TMP92CZ26A 92CZ26A-12 Table 2.2.1 Pin names and functions (5/6) 16 TMP92CZ26A 92CZ26A-13 Table 2.2.1 Pin names and functions (6/6) operational voltage TMP92CZ26A 92CZ26A-14 17 3. Operation This section describes the basic components, functions and operation of the T MP92CZ26A. 3.1 CPU The TMP92CZ26A contains an advanced high -speed 32-bit CPU (900/H1 CPU) 3.1.1 CPU Outline 18 TMP92CZ26A 92CZ26A-15 3.1.2 Reset Operation 19 TMP92CZ26A 92CZ26A-16 20 TMP92CZ26A 92CZ26A-17 21 TMP92CZ26A 92CZ26A-18 3.1.3 Setting of AM0 and AM1 TMP92CZ26A 92CZ26A-19 22 3.2 Memory Map 23 3.3 Clock Function and Standby Function 24 TMP92CZ26A 92CZ26A-21Figure 3.3.1 System clock block diagram 25 TMP92CZ26A 92CZ26A-22 Figure 3.3.2 Block Diagram of System clock 3.3.1 Block diagram of system clock 26 TMP92CZ26A 92CZ26A-23 27 TMP92CZ26A 92CZ26A-24 3.3.2 SFR 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3.3.3 SFR for system clock 28 TMP92CZ26A 92CZ26A-25 7 6 5 4 3 2 1 0 Figure 3.3.4 SFR for system clock 29 TMP92CZ26A 92CZ26A-26 30 TMP92CZ26A 92CZ26A-27 3.3.3 System clock controller 31 TMP92CZ26A 92CZ26A-28 3.3.4 Clock doubler (PLL) 32 TMP92CZ26A 92CZ26A-29 (Example-2) PLL0-stopping 33 TMP92CZ26A 92CZ26A-30 34 TMP92CZ26A 92CZ26A-31 3.3.5 Noise reduction circuits 35 TMP92CZ26A 92CZ26A-32 36 TMP92CZ26A 92CZ26A-33 37 TMP92CZ26A 92CZ26A-34 3.3.6 Standby controller 38 TMP92CZ26A 92CZ26A-35 39 TMP92CZ26A 92CZ26A-36 (interrupt level) < (interrupt mask) Halt mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP 40 TMP92CZ26A 92CZ26A-37 41 TMP92CZ26A 92CZ26A-38 42 TMP92CZ26A 92CZ26A-39 43 TMP92CZ26A 92CZ26A-40 Table 3.3.6 Input Buffer State Table Input Buffer State In HALT mode (IDLE2/1/STOP) When the CPU is operating <PxDR>=1 <PxDR>=0 Port Name Input Function Name During Reset When Used as function Pin When Used When Used as function Pin When Used as Input port When Used as function Pin When Used as Input port Always ON 44 TMP92CZ26A 92CZ26A-41 Table 3.3.7 Output buf fer State Table (1/2) Output Buffer State Port Name Output Function Name During Reset When Used as function Pin When Used as Output port When Used as function Pin When Used as Output port When Used as function Pin When Used as Output port 45 TMP92CZ26A 92CZ26A-42 Table 3.3.8 Output buf fer state table (2/2) TMP92CZ26A 92CZ26A-43 46 3.4 Boot ROM 70 3.5 Interrupts 71 TMP92CZ26A 92CZ26A-68 72 TMP92CZ26A 92CZ26A-69 3.5.1 General-purpose Interrupt Processing 73 TMP92CZ26A 92CZ26A-70to Vector Value Address Refer Micro DMA Request Vector Micro DMA /HDMA Start Vector 74 TMP92CZ26A 92CZ26A-71 75 TMP92CZ26A 92CZ26A-72 3.5.2 Micro DMA processing 76 TMP92CZ26A 92CZ26A-73 77 TMP92CZ26A 92CZ26A-74 78 TMP92CZ26A 92CZ26A-75 (4) Detailed description of the transf er mode register 0 0 0 Mode DMAM0 to 7 ZZ: 00 = 1-byte transfer 01 = 2-byte transfer 10 = 4-byte transfer 11 = Reserved 79 TMP92CZ26A 92CZ26A-76 3.5.3 Interrupt Controller Operation 80 TMP92CZ26A 92CZ26A-77 Figure 3.5.3 Block Diagram of Interrupt Controller 81 TMP92CZ26A 92CZ26A-78 82 TMP92CZ26A 92CZ26A-79 83 TMP92CZ26A 92CZ26A-80 84 TMP92CZ26A 92CZ26A-81 Interrupt request flag R R/W R R/W Symbol Name Address 7 6 5 4 3 2 1 0 INTTC1/INTDMA1 INTTC0/INTDMA0 F1H 0 0 0 0 0 0 0 0 INTTC3/INTDMA3 INTTC2/INTDMA2 F2H 0 0 0 0 0 0 0 0 INTTC5/INTDMA5 INTTC4/INTDMA4 F3H 0 0 0 0 0 0 0 0 INTTC7 (DMA7) INTTC6 (DMA6) 0 0 0 0 0 0 0 0 INTWD ITCWD R R/W R 85 TMP92CZ26A 92CZ26A-82 Symbol Name Address 7 6 5 4 3 2 1 0 DI 86 TMP92CZ26A 92CZ26A-83 87 TMP92CZ26A 92CZ26A-84 88 TMP92CZ26A 92CZ26A-85 90 TMP92CZ26A 92CZ26A-87 TMP92CZ26A 92CZ26A-88 91 3.6 DMAC (DMA Controller) 93 3.6.2 SFRs HDMASn Register 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 99 3.6.3 DMAC Operation Description 101 3.6.4 Setting Example 103 3.6.6 Considerations for Using More Than One Bus Master 107 108 TMP92CZ26A 92CZ26A-105Sample3) Calculation example for CPU + LDMA + ARDMA 109 TMP92CZ26A 92CZ26A-106 110 TMP92CZ26A 92CZ26A-107Sample 4) Calculation example for CPU + LDMA+ ARD MA + HDMA 111 TMP92CZ26A 92CZ26A-108 112 TMP92CZ26A 92CZ26A-109Sample 5) Calculation example when using CPU + LCDC + SDRAMC + HDMA at same time (Worst case) TMP92CZ26A 92CZ26A-110 113 3.7 Function of ports 183 3.8 Memory Controller (MEMC) 3.8.1 Functions 188 3.8.3 Basic functions and register setting 202 3.8.4 ROM Page mode Access Control 204 7 6 5 4 3 2 1 0 206 TMP92CZ26A 92CZ26A-203CSZA to CSZD pins dont become to active. Figure 3.8.8 Recommended CS3 setting TMP92CZ26A 92CZ26A-204 207 3.9 External Memory Extension Function (MMU) 3.9.1 Recommended memory map 208 TMP92CZ26A 92CZ26A-205 Figure 3.9.1Recommendation memory map for maximum specification (Logical address) 209 TMP92CZ26A 92CZ26A-206 LOCAL-X LOCAL-Y LOCAL-Z 92CZ26 A Note: In case of connect SDRAM to Y-area, 64MB(2MB32) is maximum Figure 3.9.2 Recommendation memo ry map for maximum specific ation (Physical address) 210 TMP92CZ26A 92CZ26A-207A Figure 3.9.4 Recommendation memory map for simple system (P hysical address) 15 Note: In case of connect SDRAM to Z-area, 64MB (4MB16) is maximum Figure 3.9.3Recommendation memory map for sim ple system (Logical address) 000000H Internal-I/O and RAM LOCAL-Z 92CZ26 SDCS Bank 0 3FE000H Internal Boot-ROM Note: In case of connect SDRAM to Z-area, 64MB(4MB16) is maxi mum 211 TMP92CZ26A 92CZ26A-208 3.9.2 Control register 212 TMP92CZ26A 92CZ26A-209 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 213 TMP92CZ26A 92CZ26A-210 214 TMP92CZ26A 92CZ26A-211 215 TMP92CZ26A 92CZ26A-212 216 TMP92CZ26A 92CZ26A-213 217 TMP92CZ26A 92CZ26A-214 218 TMP92CZ26A 92CZ26A-215 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 219 TMP92CZ26A 92CZ26A-216 220 TMP92CZ26A 92CZ26A-217 221 TMP92CZ26A 92CZ26A-218 3.9.3 Setting example 222 TMP92CZ26A 92CZ26A-219 (b) Sub routine (Bank-0 in LOCAL-Y) TMP92CZ26A 92CZ26A-220 223 3.10 SDRAM Controller (SDRAMC) 241 3.11 NAND Flash Controller (NDFC) 269 3.12 8 Bit Timer (TMRA) 274 3.12.2 Operation of Each Circuit 288 3.12.4 Operation in Each Mode 289 TMP92CZ26A 92CZ26A-286 Figure 3.12.17 Square Wave Output Timing Chart (50% duty) 290 TMP92CZ26A 92CZ26A-287 291 TMP92CZ26A 92CZ26A-288 293 TMP92CZ26A 92CZ26A-290Example: To generate 1/4 duty 31.25 kHz pulses (at fC= 50 MHz) 295 TMP92CZ26A 92CZ26A-292Figure 3.12.25 Register Buffer Operation Example: T o output the foll ow ing PWM waves o n the T A1OUT pin (at f 296 TMP92CZ26A 92CZ26A-293Table 3.12.3 PWM Cycle (5) Settings for each mode Table 3.12.4 shows the SFR settings for eac h mode. Table 3.12.4 Timer Mode Setting Registers TMP92CZ26A 92CZ26A-294 297 3.13 16 bit timer / Event counter (TMRB) 299 TMP92CZ26A 92CZ26A-296 Figure 3.13.2 Block diagram of TMRB1 TMP92CZ26A 92CZ26A-297 300 3.13.2 Operation 305 3.13.3 SFR 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Figure 3.13.3 Register for TMRB (1 ) 306 TMP92CZ26A 92CZ26A-303Figure 3.13.4 Register for TMRB (2 ) 307 TMP92CZ26A 92CZ26A-304Figure 3.13.5 Register for TMRB (3 ) 308 TMP92CZ26A 92CZ26A-305Figure 3.13.6 Register for TMRB (4 ) 310 TMP92CZ26A 92CZ26A-307Figure 3.13.8 Register for TMRB (6 ) TMP92CZ26A 92CZ26A-308 311 3.13.4 Operation in Each Mode 312 TMP92CZ26A 92CZ26A-309 313 TMP92CZ26A 92CZ26A-310The following block diagram illustrates this m ode. X: Don't care, : No change 314 TMP92CZ26A 92CZ26A-311 315 TMP92CZ26A 92CZ26A-312Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TB0IN0pin TMP92CZ26A 92CZ26A-316 319 3.14.1 Block Diagram Figure 3.14.2 Block Diagram TMP92CZ26A 92CZ26A-317 320 3.14.2 Operation of Each Circuit 324 331 3.14.3 SFR 7 6 5 4 3 2 1 0 Figure 3.14.6 Serial Mode Control Register (ch annel 0, SC0MOD0) 332 TMP92CZ26A 92CZ26A-329 7 6 5 4 3 2 1 0 Figure 3.14.7 Serial Control Register (ch annel 0, SC0CR) 333 TMP92CZ26A 92CZ26A-330 7 6 5 4 3 2 1 0 Figure 3.14.8 Baud rate generator control (channel 0, BR0CR, BR0ADD) 338 TMP92CZ26A 92CZ26A-335 339 TMP92CZ26A 92CZ26A-336 2 340 TMP92CZ26A 92CZ26A-337 346 TMP92CZ26A 92CZ26A-343 7 6 5 4 3 2 1 0 Figure 3.14.21 IrDA Control Regi ster TMP92CZ26A 92CZ26A-344 347 3.15 Serial Bus Interface (SBI) 3.15.1 Configuration 348 3.15.2 Serial Bus Interface (SBI) Control 3.15.3 The Data Formats in the I2C Bus Mode 349 3.15.4 I2C Bus Mode Control Register 350 TMP92CZ26A 92CZ26A-347 Serial Bus Interface Control Register 1 7 6 5 4 3 2 1 0 Figure 3.15.4 Registers for the I2C bus mode 351 TMP92CZ26A 92CZ26A-348 Serial Bus Interface Control Register 1 Figure 3.15.5 Registers for the I2C bus mode Table 3.15.1Resolution of base clock Clock Gea r <GEAR1:0> Base Clock Resolution 352 TMP92CZ26A 92CZ26A-349 Serial Bus Interface Status Register 7 6 5 4 3 2 1 0 Figure 3.15.6 Registers for the I2C bus mode 353 TMP92CZ26A 92CZ26A-350 TMP92CZ26A 92CZ26A-351 354 3.15.5 Control in I2C Bus Mode 369 3.16 USB Controller 460 482 3.17.2 SFR 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 494 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 496 TMP92CZ26A 92CZ26A-493 (5) SPITD (SPI Transmit Data Register) SPITD0, SPITD1 registers are for writing transmit ted data. Figure 3.17.12 SPITD Register 497 TMP92CZ26A 92CZ26A-494(6) SPIRD (SPI Receiv e Data Register) SPIRD0, SPIRD1 registers are for reading received data. Figure 3.17.13 SPIRD register TMP92CZ26A 498 Note of FIFO buffer 499 3.18 I2S (Inter-IC Sound) 500 TMP92CZ26A 92CZ26A-497 3.18.1 Block Diagram TMP92CZ26A 92CZ26A-498 501 Figure 3.18.2 I2S Channel 0 Control Re gisters TMP92CZ26A 92CZ26A-499 502 511 3.19 LCD Controller (LCDC) 567 3.20 Touch Screen Interface (TSI) 3.20.1 Touch-Screen Interface Module Internal/External Connection 577 3.21 Real time clock (RTC) 592 3.22 Melody / Alarm generator (MLD) 593 TMP92CZ26A 92CZ26A-590 3.22.1 Block Diagram 594 TMP92CZ26A 92CZ26A-591 3.22.2 Control registers ALM register 7 6 5 4 3 2 1 0 MELALMC register 7 6 5 4 3 2 1 0 MELFL register 7 6 5 4 3 2 1 0 MELFH register 7 6 5 4 3 2 1 0 ALMINT register 7 6 5 4 3 2 1 0 595 TMP92CZ26A 92CZ26A-592 3.22.3 Operational Description 596 TMP92CZ26A 92CZ26A-593 597 TMP92CZ26A 92CZ26A-594 Example: Waveform of alarm pattern for each setting value: not invert) TMP92CZ26A 92CZ26A-595 598 3.23 Analog-Digital Converter (ADC) 618 3.24 Watchdog Timer (Runaway detection timer) 3.24.1 Configuration 619 TMP92CZ26A 92CZ26A-616 3.24.2 Operation 620 TMP92CZ26A 92CZ26A-617 3.24.3 Control Registers 621 TMP92CZ26A 92CZ26A-618 7 6 5 4 3 2 1 0 Figure 3.24.4 Watchdog Timer Mo de Register 7 6 5 4 3 2 1 0 Figure 3.24.5 Watchdog Timer Control Regi ster TMP92CZ26A 92CZ26A-619 622 3.25 Power Management Circuit (PMC) 631 3.26 Multiply and Accumulate Calculation Unit (MAC) 3.26.1 Registers 632 TMP92CZ26A 92CZ26A-629 3.26.1.2 Data Registers The data registers are arranged as shown below. 633 TMP92CZ26A 92CZ26A-630 3.26.2 Description of Operation 634 TMP92CZ26A 92CZ26A-631 635 TMP92CZ26A 92CZ26A-632 3.26.3 Operation Examples TMP92CZ26A 92CZ26A-633 636 3.27 Debug Mode 643 4. Electrical Characteristics (Tentative) 668 5. Table of Special function registers (SFRs) 669 TMP92CZ26A 92CZ26A-666 Table 5.1 I/O Register Address Map [1] Port (1/2) 670 TMP92CZ26A 92CZ26A-667 671 TMP92CZ26A 92CZ26A-668 [2] INTC [3] MEMC [4] TSI Note: Do not access no allocated name address. 672 TMP92CZ26A 92CZ26A-669 [5] SDRAMC [6] LCDC [7] PMC Address Name Address Name Address Name Address Name Note: Do not access no allocated name address. 673 TMP92CZ26A 92CZ26A-670 [8] USBC (1/2) Address Name Address Name Address Name Address Name Address Name Address Name Address Name Note: Do not access no allocated name address. 674 TMP92CZ26A 92CZ26A-671 675 TMP92CZ26A 92CZ26A-672 [9] SPIC Address Name Address Name [10] MMU Address Name Address Name Address Name Address Name Note: Do not access no allocated name address. 676 TMP92CZ26A 92CZ26A-673 677 TMP92CZ26A 92CZ26A-674 [12] DMAC Address Name Address Name Address Name Address Name Address Name Address Name Address Name 678 TMP92CZ26A 92CZ26A-675 [13] CGEAR, PLL [14] 8-bit timer Address Name Address Name Address Name Address Name Address Name Address Name Address Name Note: Do not access no allocated name address. 679 TMP92CZ26A 92CZ26A-676 680 TMP92CZ26A 92CZ26A-677 [22] I2S [23] MAC Note: Do not access no allocated name address. 681 TMP92CZ26A 92CZ26A-678 (1) I/O ports (1/11) Symbol Name 682 TMP92CZ26A 92CZ26A-679 (1) I/O ports (2/11) Symbol Name 683 TMP92CZ26A 92CZ26A-680 (1) I/O ports (3/11) Symbol Name 684 TMP92CZ26A 92CZ26A-681 (1) I/O ports (4/11) Symbol Name 685 TMP92CZ26A 92CZ26A-682 (1) I/O ports (5/11) Symbol Name 686 TMP92CZ26A 92CZ26A-683 (1) I/O ports (6/11) Symbol Name 687 TMP92CZ26A 92CZ26A-684 (1) I/O ports (7/11) Symbol Name 688 TMP92CZ26A 92CZ26A-685 (1) I/O ports (8/11) Symbol Name 689 TMP92CZ26A 92CZ26A-686 (1) I/O ports (9/11) Symbol Name 690 TMP92CZ26A 92CZ26A-687 691 TMP92CZ26A 92CZ26A-688 692 TMP92CZ26A 92CZ26A-689 (2) Interrupt control (1/4) 693 TMP92CZ26A 92CZ26A-690 (2) Interrupt control (2/4) Symbol Name 694 TMP92CZ26A 92CZ26A-691 (2) Interrupt control (3/4) Symbol Name 695 TMP92CZ26A 92CZ26A-692 (2) Interrupt control (4/4) Symbol Name 696 TMP92CZ26A 92CZ26A-693 (3) Memory controller (1/4) Symbol Name 697 TMP92CZ26A 92CZ26A-694 (3) Memory controller (2/4) Symbol Name 698 TMP92CZ26A 92CZ26A-695 (3) Memory controller (3/4) Symbol Name 699 TMP92CZ26A 92CZ26A-696 (3) Memory controller (4/4) Symbol Name 700 TMP92CZ26A 92CZ26A-697 701 TMP92CZ26A 92CZ26A-698 (5) SDRAM controller Symbol Name 702 TMP92CZ26A 92CZ26A-699 (6) LCD controller (1/6) Symbol Name 703 TMP92CZ26A 92CZ26A-700 (6) LCD controller (2/6) Symbol Name 704 TMP92CZ26A 92CZ26A-701 (6) LCD controller (3/6) Symbol Name 705 TMP92CZ26A 92CZ26A-702 (6) LCD controller (4/6) Symbol Name 706 TMP92CZ26A 92CZ26A-703 707 TMP92CZ26A 92CZ26A-704 (8) USB controller (1/6) Symbol Name 708 TMP92CZ26A 92CZ26A-705 (8) USB control ler (2/6) Symbol Name 709 TMP92CZ26A 92CZ26A-706 (8) USB control ler (3/6) Symbol Name 710 TMP92CZ26A 92CZ26A-707 (8) USB control ler (4/6) Symbol Name 711 TMP92CZ26A 92CZ26A-708 (8) USB control ler (5/6) Symbol Name 712 TMP92CZ26A 92CZ26A-709 (8) USB control ler (6/6) Symbol Name 713 TMP92CZ26A 92CZ26A-710 (9) SPIC (1/2) Symbol Name 714 TMP92CZ26A 92CZ26A-711 (9) SPIC (2/2) Symbol Name 715 TMP92CZ26A 92CZ26A-712 (10) MMU (1/8) Symbol Name 716 TMP92CZ26A 92CZ26A-713 (10) MMU (2/8) Symbol Name 717 TMP92CZ26A 92CZ26A-714 (10) MMU (3/8) Symbol Name 718 TMP92CZ26A 92CZ26A-715 (10) MMU (4/8) Symbol Name 719 TMP92CZ26A 92CZ26A-716 (10) MMU (5/8) Symbol Name 720 TMP92CZ26A 92CZ26A-717 (10) MMU (6/8) Symbol Name 721 TMP92CZ26A 92CZ26A-718 (10) MMU (7/8) Symbol Name 722 TMP92CZ26A 92CZ26A-719 (10) MMU (8/8) Symbol Name 723 TMP92CZ26A 92CZ26A-720 (11) NAND-Flash contro ller (1/4) Symbol Name 724 TMP92CZ26A 92CZ26A-721 (11) NAND-Flash contro ller (2/4) Symbol Name 725 TMP92CZ26A 92CZ26A-722 (11) NAND-Flash contro ller (3/4) Symbol Name 726 TMP92CZ26A 92CZ26A-723 (11) NAND-Flash contro ller (4/4) Symbol Name 727 TMP92CZ26A 92CZ26A-724 (12) DMAC (1/7) Symbol Name 728 TMP92CZ26A 92CZ26A-725 (12) DMAC (2/7) Symbol Name 729 TMP92CZ26A 92CZ26A-726 (12) DMAC (3/7) Symbol Name 730 TMP92CZ26A 92CZ26A-727 (12) DMAC (4/7) Symbol Name 731 TMP92CZ26A 92CZ26A-728 (12) DMAC (5/7) Symbol Name 732 TMP92CZ26A 92CZ26A-729 (12) DMAC (6/7) Symbol Name 733 TMP92CZ26A 92CZ26A-730 (12) DMAC (7/7) Symbol Name 734 TMP92CZ26A 92CZ26A-731 (13) Clock gear, PLL Symbol Name 735 TMP92CZ26A 92CZ26A-732 (14) 8-bit timer (1/2) Symbol Name 736 TMP92CZ26A 92CZ26A-733 (14) 8-bit timer (1/2) Symbol Name 737 TMP92CZ26A 92CZ26A-734 (15) 16-bit timer (1/2) Symbol Name 738 TMP92CZ26A 92CZ26A-735 (15) 16-bit timer (2/2) Symbol Name 739 TMP92CZ26A 92CZ26A-736 (16) UART/Serial channel s Symbol Name 740 TMP92CZ26A 92CZ26A-737 (17) SBI Symbol Name Address 7 6 5 4 3 2 1 0 741 TMP92CZ26A 92CZ26A-738 (18) AD converter (1/3) Symbol Name 742 TMP92CZ26A 92CZ26A-739 (18) AD converter (2/3) Symbol Name 743 TMP92CZ26A 92CZ26A-740 (18) AD converter (3/3) Symbol Name ADMOD3 AD mode control register 0 12B8H DACON ADCH2 ADCH1 ADCH0 LAT ITM REPEAT SCAN R/W 0 0 0 0 0 0 0 0 ADMOD1 AD mode control register 1 12B9H HEOS HBUSY HADS HHTRGE HTSEL1 HTSEL0 R R/W 0 0 0 0 0 0 ADMOD2 AD mode control register 2 12BAH R/W 0 0 0 0 control register 3 12BBH High-priority analog input channel select CMCH2 CM1CH1 CM1CH0 CM0CH2 CM0CH1 CM0CH0 R/W R/W 0 0 0 0 0 0 ADMOD5 AD mode control register 5 12BDH 744 TMP92CZ26A 92CZ26A-741 (19) Watchdog timer Symbol Name 745 TMP92CZ26A 92CZ26A-742 (20) RTC (Real-Time Clock) Symbol Name 746 TMP92CZ26A 92CZ26A-743 (21) Melody/alarm generator Symbol Name 747 TMP92CZ26A 92CZ26A-744 (22) I2S (1/2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 748 TMP92CZ26A 92CZ26A-745 (22) I2S (2/2) Symbol Name 749 TMP92CZ26A 92CZ26A-746 (23) MAC (1/ 2 ) Symbol Name 750 TMP92CZ26A 92CZ26A-747 (23) MAC (2/ 2 ) Symbol Name 751 6. Package
260 pages 1.84 Mb
Also you can find more Toshiba manuals or manuals for other Computer Equipment.