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ii Intel PXA255 Processor Developers Manual
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Intel PXA255 Processor Developers Manual xxiii
Contents
Revision History
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Introduction 1
1.1 Intel XScale Microarchitecture Features
1.2 System Integration Features
1.2.1 Memory Controller
1.2.2 Clocks and Power Controllers
1.2.3 Universal Serial Bus (USB) Client
1.2.4 DMA Controller (DMAC)
1.2.5 LCD Controller
1.2.6 AC97 Controller
1.2.7 Inter-IC Sound (I2S) Controller
1.2.8 Multimedia Card (MMC) Controller
1.2.10 Synchronous Serial Protocol Controller (SSPC)
1.2.11 Inter-Integrated Circuit (I2C) Bus Interface Unit
1.2.12 GPIO
1.2.13 UARTs
1.2.13.1 Full Function UART (FFUART)
1.2.14 Real-Time Clock (RTC)
1.2.15 OS Timers
1.2.16 Pulse-Width Modulator (PWM)
1.2.17 Interrupt Control
1.2.18 Network Synchronous Serial Protocol Port
Page
System Architecture 2
2.1 Overview
2-2 Intel PXA255 Processor Developers Manual
2.2 Intel XScale Microarchitecture Implementation Options
2.2.1 Coprocessor 7 Register 4 - PSFS Bit
Figure 2-1. Block Diagram
2.2.2 Coprocessor 14 Registers 0-3 - Performance Monitoring
2.2.3 Coprocessor 14 Register 6 and 7- Clock and Power Management
2.2.4 Coprocessor 15 Register 0 - ID Register Definition
2.2.5 Coprocessor 15 Register 1 - P-Bit
2.3 I/O Ordering
2.4 Semaphores
2.5 Interrupts
2.6 Reset
2.7 Internal Registers
2.8 Selecting Peripherals vs. General Purpose I/O
2.9 Power on Reset and Boot Operation
2.10 Power Management
2.11 Pin List
Table 2-6 describes the PXA255 processor pins.
Intel PXA255 Processor Developers Manual 2-9
Table 2-5. Processor Pin Types
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)
2-10 Intel PXA255 Processor Developers Manual
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 2 of 9)
Intel PXA255 Processor Developers Manual 2-11
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 3 of 9)
2-12 Intel PXA255 Processor Developers Manual
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)
Intel PXA255 Processor Developers Manual 2-13
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 5 of 9)
2-14 Intel PXA255 Processor Developers Manual
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 9)
Intel PXA255 Processor Developers Manual 2-15
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)
2-16 Intel PXA255 Processor Developers Manual
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 8 of 9)
Intel PXA255 Processor Developers Manual 2-17
Table 2-7. Pin Description Notes (Sheet 1 of 2)
Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 9 of 9)
2.12 Memory Map
Intel PXA255 Processor Developers Manual 2-19
Figure 2-2. Memory Map (Part One) From 0x8000_0000 to 0xFFFF FFFF
2-20 Intel PXA255 Processor Developers Manual
Figure 2-3. Memory Map (Part Two) From 0x0000_0000 to 0x7FFF FFFF
Intel PXA255 Processor Developers Manual 2-21
2.13 System Architecture Register Summary
Table 2-8. System Architecture Register Address Summary (Sheet 1 of 12)
2-22 Intel PXA255 Processor Developers Manual
Table 2-8. System Architecture Register Address Summary (Sheet 2 of 12)
Intel PXA255 Processor Developers Manual 2-23
Table 2-8. System Architecture Register Address Summary (Sheet 3 of 12)
2-24 Intel PXA255 Processor Developers Manual
Table 2-8. System Architecture Register Address Summary (Sheet 4 of 12)
Intel PXA255 Processor Developers Manual 2-25
Table 2-8. System Architecture Register Address Summary (Sheet 5 of 12)
2-26 Intel PXA255 Processor Developers Manual
Table 2-8. System Architecture Register Address Summary (Sheet 6 of 12)
Intel PXA255 Processor Developers Manual 2-27
Table 2-8. System Architecture Register Address Summary (Sheet 7 of 12)
2-28 Intel PXA255 Processor Developers Manual
Table 2-8. System Architecture Register Address Summary (Sheet 8 of 12)
Intel PXA255 Processor Developers Manual 2-29
Table 2-8. System Architecture Register Address Summary (Sheet 9 of 12)
2-30 Intel PXA255 Processor Developers Manual
Table 2-8. System Architecture Register Address Summary (Sheet 10 of 12)
Intel PXA255 Processor Developers Manual 2-31
Table 2-8. System Architecture Register Address Summary (Sheet 11 of 12)
2-32 Intel PXA255 Processor Developers Manual
Table 2-8. System Architecture Register Address Summary (Sheet 12 of 12)
Clocks and Power Manager 3
3.1 Clock Manager Introduction
3.2 Power Manager Introduction
3.3 Clock Manager
Page
3.3.1 32.768 kHz Oscillator
3.3.2 3.6864 MHz Oscillator
3.3.3 Core Phase Locked Loop
3.3.4 95.85 MHz Peripheral Phase Locked Loop
3.3.5 147.46 MHz Peripheral Phase Locked Loop
3.3.6 Clock Gating
3.4 Resets and Power Modes
3.4.1 Hardware Reset
3.4.1.1 Invoking Hardware Reset
3.4.1.2 Behavior During Hardware Reset
3.4.1.3 Completing Hardware Reset
3.4.2 Watchdog Reset
3.4.2.1 Invoking Watchdog Reset
3.4.2.2 Behavior During Watchdog Reset
3.4.2.3 Completing a Watchdog Reset
3.4.3 GPIO Reset
3.4.3.1 Invoking GPIO Reset
3.4.3.2 Behavior During GPIO Reset
3.4.3.3 Completing GPIO Reset
3.4.4 Run Mode
3.4.5 Turbo Mode
3.4.5.1 Entering Turbo Mode
3.4.5.2 Behavior in Turbo Mode
3.4.5.3 Exiting Turbo Mode
3.4.6 Idle Mode
3.4.6.1 Entering Idle Mode
3.4.6.2 Behavior in Idle Mode
3.4.6.3 Exiting Idle Mode
3.4.7 Frequency Change Sequence
3.4.7.1 Preparing for a Frequency Change Sequence
3.4.7.2 Invoking the Frequency Change Sequence
3.4.7.3 Behavior During the Frequency Change Sequence
3.4.7.4 Completing the Frequency Change Sequence
3.4.8 33-MHz Idle Mode
Page
3.4.8.3 Exiting 33-MHz Idle Mode
3.4.9 Sleep Mode
3.4.9.1 Sleep Mode External Voltage Regulator Requirements
3.4.9.2 Preparing for Sleep Mode
3.4.9.3 Entering Sleep Mode
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3.4.9.4 Behavior in Sleep Mode
3.4.9.5 Exiting Sleep Mode
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3-20 Intel PXA255 Processor Developers Manual
3.4.10 Power Mode Summary
Table 3-4. Power Mode Entry Sequence Table
Table 3-5. Power Mode Exit Sequence Table (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 3-21
Table 3-5. Power Mode Exit Sequence Table (Sheet 2 of 2)
3-22 Intel PXA255 Processor Developers Manual
3.5 Power Manager Registers
This section describes the 32-bit registers that control the Power Manager.
Table 3-6. Power and Clock Supply Sources and States During Power Modes
3.5.1 Power Manager Control Register (PMCR)
3.5.2 Power Manager General Configuration Register (PCFR)
3.5.3 Power Manager Wake-Up Enable Register (PWER)
3.5.4 Power Manager Rising-Edge Detect Enable Register (PRER)
3.5.5 Power Manager Falling-Edge Detect Enable Register (PFER)
3.5.6 Power Manager GPIO Edge Detect Status Register (PEDR)
3.5.7 Power Manager Sleep Status Register (PSSR)
3-30 Intel PXA255 Processor Developers Manual
3.5.8 Power Manager Scratch Pad Register (PSPR)
Table 3-13. PSSR Bit Definitions (Sheet 2 of 2)
Table 3-14. PSPR Bit Definitions
3.5.9 Power Manager Fast Sleep Walk-up Configuration Register (PMFW)
3.5.10 Power Manager GPIO Sleep State Registers (PGSR0, PGSR1, PGSR2)
3-32 Intel PXA255 Processor Developers Manual
Table 3-16. PGSR0 Bit Definitions
Table 3-17. PGSR1 Bit Definitions
3.5.11 Reset Controller Status Register (RCSR)
3.6 Clocks Manager Registers
3.6.1 Core Clock Configuration Register (CCCR)
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3-36 Intel PXA255 Processor Developers Manual
3.6.2 Clock Enable Register (CKEN)
Table 3-21. CKEN Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 3-37
Table 3-21. CKEN Bit Definitions (Sheet 2 of 2)
3.6.3 Oscillator Configuration Register (OSCC)
3.7 Coprocessor 14: Clock and Power Management
3.7.1 Core Clock Configuration Register (CCLKCFG)
3.7.2 Power Mode Register (PWRMODE)
3.8 External Hardware Considerations
3.8.1 Power-On-Reset Considerations
3.8.2 Power Supply Connectivity
3.8.3 Driving the Crystal Pins from an External Clock Source
3.8.4 Noise Coupling Between Driven Crystal Pins and a Crystal Oscillator
3.9 Clocks and Power Manager Register Summary
3.9.1 Clocks Manager Register Locations
3.9.2 Power Manager Register Summary
3-42 Intel PXA255 Processor Developers Manual
Table 3-27. Power Manager Register Summary
System Integration Unit 4
4.1 General-Purpose I/O
4.1.1 GPIO Operation
4.1.2 GPIO Alternate Functions
Intel PXA255 Processor Developers Manual 4-3
4-4 Intel PXA255 Processor Developers Manual
Table 4-1. GPIO Alternate Functions (Sheet 2 of 4)
Intel PXA255 Processor Developers Manual 4-5
Table 4-1. GPIO Alternate Functions (Sheet 3 of 4)
4.1.3 GPIO Register Definitions
Intel PXA255 Processor Developers Manual 4-7
4.1.3.1 GPIO Pin-Level Registers (GPLR0, GPLR1, GPLR2)
This is read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 4-2. GPIO Register Definitions (Sheet 2 of 2)
Table 4-3. GPLR0 Bit Definitions
4-8 Intel PXA255 Processor Developers Manual
4.1.3.2 GPIO Pin Direction Registers (GPDR0, GPDR1, GPDR2)
Table 4-4. GPLR1 Bit Definitions
Table 4-5. GPLR2 Bit Definitions
Intel PXA255 Processor Developers Manual 4-9
Table 4-6. GPDR0 Bit Definitions
Table 4-7. GPDR1 Bit Definitions
Table 4-8. GPDR2 Bit Definitions
4-10 Intel PXA255 Processor Developers Manual
Table 4-10. GPSR1 Bit Definitions
Intel PXA255 Processor Developers Manual 4-11
Table 4-11. GPSR2 Bit Definitions
Table 4-12. GPCR0 Bit Definitions
Table 4-13. GPCR1 Bit Definitions
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Intel PXA255 Processor Developers Manual 4-13
Table 4-15. GRER0 Bit Definitions
Table 4-16. GRER1 Bit Definitions
Table 4-17. GRER2 Bit Definitions
4-14 Intel PXA255 Processor Developers Manual
Table 4-18. GFER0 Bit Definitions
Table 4-19. GFER1 Bit Definitions
Table 4-20. GFER2 Bit Definitions
Intel PXA255 Processor Developers Manual 4-15
4.1.3.5 GPIO Edge Detect Status Register (GEDR0, GEDR1, GEDR2)
Table 4-22. GEDR1 Bit Definitions
4.1.3.6 GPIO Alternate Function Register (GAFR0_L, GAFR0_U, GAFR1_L, GAFR1_U, GAFR2_L, GAFR2_U)
Intel PXA255 Processor Developers Manual 4-17
Table 4-25. GAFR0_U Bit Definitions
4-18 Intel PXA255 Processor Developers Manual
Table 4-26. GAFR1_L Bit Definitions
Table 4-27. GAFR1_U Bit Definitions
4.1.3.7 Example Procedure for Configuring the Alternate Function Registers
4.2 Interrupt Controller
4.2.1 Interrupt Controller Operation
4.2.2 Interrupt Controller Register Definitions
4.2.2.1 Interrupt Controller Mask Register (ICMR)
4.2.2.2 Interrupt Controller Level Register (ICLR)
Intel PXA255 Processor Developers Manual 4-23
4.2.2.3 Interrupt Controller Control Register (ICCR)
Table 4-31. ICLR Bit Definitions
Table 4-32. ICCR Bit Definitions
4-24 Intel PXA255 Processor Developers Manual
4.2.2.4 Interrupt Controller IRQ Pending Register (ICIP) and FIQ Pending Register (ICFP)
Table 4-34. ICFP Bit Definitions
Intel PXA255 Processor Developers Manual 4-25
4.2.2.5 Interrupt Controller Pending Register (ICPR)
4-26 Intel PXA255 Processor Developers Manual
Table 4-35. ICPR Bit Definitions (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 4-27
Table 4-36. List of FirstLevel Interrupts (Sheet 1 of 2)
Table 4-35. ICPR Bit Definitions (Sheet 3 of 3)
4.3 Real-Time Clock (RTC)
4.3.1 Real-Time Clock Operation
4.3.2 RTC Register Definitions
4.3.2.1 RTC Trim Register (RTTR)
4.3.2.2 RTC Alarm Register (RTAR)
4.3.2.3 RTC Counter Register (RCNR)
4.3.2.4 RTC Status Register (RTSR)
4.3.3 Trim Procedure
4.3.3.1 Oscillator Frequency Calibration
4.3.3.2 RTTR Value Calculations
3276 8
4.4 Operating System (OS) Timer
4.4.1 Watchdog Timer Operation
4.4.2 OS Timer Register Definitions
4.4.2.1 OS Timer Match Register 0-3 (OSMRx)
4-36 Intel PXA255 Processor Developers Manual
4.4.2.2 OS Timer Interrupt Enable Register (OIER)
Table 4-41. OSMR[x] Bit Definitions
Table 4-42. OIER Bit Definitions
4.4.2.3 OS Timer Watchdog Match Enable Register (OWER)
4.4.2.4 OS Timer Count Register (OSCR)
4.4.2.5 OS Timer Status Register (OSSR)
4.5 Pulse Width Modulator
4.5.1 Pulse Width Modulator Operation
4.5.1.1 Interdependencies
4.5.1.2 Reset Sequence
4.5.1.3 Power Management Requirements
4.5.2 Register Descriptions
4.5.2.1 PWM Control Registers (PWM_CTRLn)
4.5.2.2 PWM Duty Cycle Registers (PWM_DUTYn)
4.5.2.3 PWM Period Control Register (PWM_PERVALn)
4.5.3 Pulse Width Modulator Output Wave Example
4-44 Intel PXA255 Processor Developers Manual
4.6 System Integration Unit Register Summary
4.6.1 GPIO Register Locations
4.6.2 Interrupt Controller Register Locations
4.6.3 Real-Time Clock Register Locations
4.6.4 OS Timer Register Locations
4.6.5 Pulse Width Modulator Register Locations
DMA Controller 5
5.1 DMA Description
5.1.1 DMAC Channels
5.1.2 Signal Descriptions
5.1.2.1 DREQ[1:0] and PREQ[37:0] Signals
5.1.2.2 DMA_IRQ Signal
5.1.3 DMA Channel Priority Scheme
Page
5.1.4 DMA Descriptors
5.1.4.1 No-Descriptor Fetch Mode
5.1.4.2 Descriptor Fetch Mode
Page
5.1.4.3 Servicing an Interrupt
5.1.5 Channel States
5.1.6 Read and Write Order
5.1.7 Byte Transfer Order
5.1.8 Trailing Bytes
5.2 Transferring Data
5.2.1 Servicing Internal Peripherals
Page
Intel PXA255 Processor Developers Manual 5-13
5.2.2 Quick Reference for DMA Programming
5.2.3 Servicing Companion Chips and External Peripherals
Page
5.2.4 Memory-to-Memory Moves
5.3 DMAC Registers
5.3.1 DMA Interrupt Register (DINT)
5.3.2 DMA Channel Control/Status Register (DCSRx)
5-18 Intel PXA255 Processor Developers Manual
Table 5-7. DCSRx Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 5-19
Table 5-7. DCSRx Bit Definitions (Sheet 2 of 2)
5.3.3 DMA Request to Channel Map Registers (DRCMRx)
5.3.4 DMA Descriptor Address Registers (DDADRx)
5.3.5 DMA Source Address Registers
5.3.6 DMA Target Address Registers (DTADRx)
5.3.7 DMA Command Registers (DCMDx)
5-24 Intel PXA255 Processor Developers Manual
Table 5-12. DCMDx Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 5-25
Table 5-12. DCMDx Bit Definitions (Sheet 2 of 2)
5.4 Examples
Page
5.5 DMA Controller Register Summary
Intel PXA255 Processor Developers Manual 5-29
Table 5-13. DMA Controller Register Summary (Sheet 2 of 5)
5-30 Intel PXA255 Processor Developers Manual
Table 5-13. DMA Controller Register Summary (Sheet 3 of 5)
Intel PXA255 Processor Developers Manual 5-31
Table 5-13. DMA Controller Register Summary (Sheet 4 of 5)
Page
Memory Controller 6
6.1 Overview
6-2 Intel PXA255 Processor Developers Manual
6.2 Functional Description
6.2.1 SDRAM Interface Overview
Figure 6-1. General Memory Interface Configuration
6.2.2 Static Memory Interface / Variable Latency I/O Interface
6.2.3 16-Bit PC Card / Compact Flash Interface
6.3 Memory System Examples
Intel PXA255 Processor Developers Manual 6-5
Figure 6-2. SDRAM Memory System Example
6-6 Intel PXA255 Processor Developers Manual
6.4 Memory Accesses
6.4.1 Reads and Writes
6.4.2 Aborts and Nonexistent Memory
6.5 Synchronous DRAM Memory Interface
6.5.1 SDRAM MDCNFG Register (MDCNFG
Intel PXA255 Processor Developers Manual 6-9
Table 6-2. MDCNFG Bit Definitions (Sheet 1 of 3)
6-10 Intel PXA255 Processor Developers Manual
Table 6-2. MDCNFG Bit Definitions (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 6-11
Table 6-2. MDCNFG Bit Definitions (Sheet 3 of 3)
6.5.2 SDRAM Mode Register Set Configuration Register (MDMRS)
6.5.2.1 Low-Power SDRAM Mode Register Set Configuration Register
6.5.3 SDRAM MDREFR Register (MDREFR)
Intel PXA255 Processor Developers Manual 6-15
Table 6-5. MDREFR Bit Definitions (Sheet 1 of 3)
6-16 Intel PXA255 Processor Developers Manual
Table 6-5. MDREFR Bit Definitions (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 6-17
6.5.4 Fixed-Delay or Return-Clock Data Latching
Table 6-5. MDREFR Bit Definitions (Sheet 3 of 3)
6.5.5 SDRAM Memory Options
6.5.5.1 SDRAM Addressing Modes
Page
6-20 Intel PXA255 Processor Developers Manual
Table 6-7. External to Internal Address Mapping for Normal Bank Addressing (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 6-21
Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 1 of 3)
Table 6-7. External to Internal Address Mapping for Normal Bank Addressing (Sheet 3 of 3)
6-22 Intel PXA255 Processor Developers Manual
Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 6-23
Table 6-8. External to Internal Address Mapping for SA-1111 Addressing (Sheet 3 of 3)
Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 1 of 3)
6-24 Intel PXA255 Processor Developers Manual
Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 6-25
Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 1 of 3)
Table 6-9. Pin Mapping to SDRAM Devices with Normal Bank Addressing (Sheet 3 of 3)
6-26 Intel PXA255 Processor Developers Manual
Table 6-10. Pin Mapping to SDRAM Devices with SA1111 Addressing (Sheet 2 of 3)
6.5.6 SDRAM Command Overview
6-28 Intel PXA255 Processor Developers Manual
6.5.7 SDRAM Waveforms
Normal operation of the SDRAM controller is shown in Figure 6-5 through Figure 6-11.
Table 6-11. SDRAM Command Encoding
Table 6-12. SDRAM Mode Register Opcode Table
Intel PXA255 Processor Developers Manual 6-29
Figure 6-5. Basic SDRAM Timing Parameters
Figure 6-6. SDRAM_Read_diffbank_diffrow
6-30 Intel PXA255 Processor Developers Manual
Figure 6-7. SDRAM_read_samebank_diffrow
Figure 6-8. SDRAM_read_samebank_samerow
Intel PXA255 Processor Developers Manual 6-31
Figure 6-9. SDRAM_write
Figure 6-10. SDRAM 4-Beat Read/ 4-Beat Write To Different Partitions
0 1 1
6.6 Synchronous Static Memory Interface
6.6.1 Synchronous Static Memory Configuration Register (SXCNFG)
Intel PXA255 Processor Developers Manual 6-33
Table 6-13. SXCNFG Bit Definitions (Sheet 1 of 4)
6-34 Intel PXA255 Processor Developers Manual
Table 6-13. SXCNFG Bit Definitions (Sheet 2 of 4)
Intel PXA255 Processor Developers Manual 6-35
Table 6-13. SXCNFG Bit Definitions (Sheet 3 of 4)
6-36 Intel PXA255 Processor Developers Manual
6.6.1.1 SMROM Memory Options
Table 6-13. SXCNFG Bit Definitions (Sheet 4 of 4)
6.6.2 Synchronous Static Memory Mode Register Set Configuration Register (SXMRS)
6.6.3 Synchronous Static Memory Timing Diagrams
6.6.4 Non-SDRAM Timing SXMEM Operation
6-40 Intel PXA255 Processor Developers Manual
Table 6-17. Read Configuration Register Programming Values
Table 6-18. Frequency Code Configuration Values Based on Clock Speed (Sheet 1 of 2)
6.6.4.1 Non-SDRAM Timing Flash Read Timing Diagram
6.6.4.2 K3 Synchronous StrataFlash Reset
6.7 Asynchronous Static Memory
6.7.1 Static Memory Interface
Page
6.7.2 Static Memory SA-1111 Compatibility Configuration Register (SA1111CR)
Intel PXA255 Processor Developers Manual 6-45
Table 6-21. 32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0]
Table 6-22. 16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0]
Table 6-23. SA-1111 Register Bit Definitions
6.7.3 Asynchronous Static Memory Control Registers (MSCx)
Intel PXA255 Processor Developers Manual 6-47
Table 6-24. MSC0/1/2 Bit Definitions (Sheet 1 of 3)
6-48 Intel PXA255 Processor Developers Manual
Table 6-24. MSC0/1/2 Bit Definitions (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 6-49
Table 6-24. MSC0/1/2 Bit Definitions (Sheet 3 of 3)
6-50 Intel PXA255 Processor Developers Manual
Table 6-25 provides a comparison of supported Asynchronous Static Memory types.
6.7.4 ROM Interface
Table 6-25. Asynchronous Static Memory and Variable Latency I/O Capabilities
Intel PXA255 Processor Developers Manual 6-51
6.7.4.1 ROM Timing Diagrams and Parameters
6-52 Intel PXA255 Processor Developers Manual
6.7.5 SRAM Interface Overview
6.7.5.1 SRAM Timing Diagrams and Parameters
6.7.6 Variable Latency I/O (VLIO) Interface Overview
6-56 Intel PXA255 Processor Developers Manual
6.7.6.1 Variable Latency I/O Timing Diagrams and Parameters
6.7.7 FLASH Memory Interface
Intel PXA255 Processor Developers Manual 6-59
In Figure 6-23 some of the parameters are defined as follows:
Figure 6-23. Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes)
6.8 16-Bit PC Card/Compact Flash Interface
6.8.1 Expansion Memory Timing Configuration Register
Intel PXA255 Processor Developers Manual 6-61
Table 6-27. MCATT0/1 Bit Definitions
Table 6-28. MCIO0/1 Bit Definitions
6-62 Intel PXA255 Processor Developers Manual
Table 6-29. Card Interface Command Assertion Code Table
Intel PXA255 Processor Developers Manual 6-63
6.8.2 Expansion Memory Configuration Register (MECR)
Table 6-29. Card Interface Command Assertion Code Table
Table 6-30. MECR Bit Definition
6.8.3 16-Bit PC Card Overview
Page
6.8.4 External Logic for 16-Bit PC Card Implementation
Intel PXA255 Processor Developers Manual 6-67
Figure 6-27. Expansion Card External Logic for a One-Socket Configuration
6-68 Intel PXA255 Processor Developers Manual
Figure 6-28. Expansion Card External Logic for a Two-Socket Configuration
PXA255 Processor
Socket 1
Socket 0
6.8.5 Expansion Card Interface Timing Diagrams and Parameters
6.9 Companion Chip Interface
Figure 6-31. Alternate Bus Master Mode
Figure 6-32. Variable Latency IO
6.9.1 Alternate Bus Master Mode
6.9.1.1 GPIO Reset
6.9.1.2 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Disabled
6.9.1.3 nVDD_FAULT/nBATT_FAULT with PMCR[IDAE] Enabled
6.10 Options and Settings for Boot Memory
6.10.1 Alternate Booting
6.10.2 Boot Time Defaults
6.10.2.1 BOOT_DEF Read-Only Register (BOOT_DEF)
Intel PXA255 Processor Developers Manual 6-75
Table 6-40. BOOT_DEF Bitmap
Table 6-41. Valid Boot Configurations Based on Processor Type
6-76 Intel PXA255 Processor Developers Manual
6.10.2.2 Boot-Time Configurations
Intel PXA255 Processor Developers Manual 6-77
Figure 6-34. SMROM Boot Time Configurations and Register Defaults
6-78 Intel PXA255 Processor Developers Manual
6.10.3 Memory Interface Reset and Initialization
Figure 6-35. SMROM Boot Time Configurations and Register Defaults
6.11 Hardware, Watchdog, or Sleep Reset Operation
Page
6.12 GPIO Reset Procedure
6.13 Memory Controller Register Summary
Page
LCD Controller 7
7.1 Overview
7.1.1 Features
Intel PXA255 Processor Developers Manual 7-3
7.1.2 Pin Descriptions
7.2 LCD Controller Operation
7.2.1 Enabling the Controller
7.2.2 Disabling the Controller
7.2.3 Resetting the Controller
7.3 Detailed Module Descriptions
7.3.1 Input FIFOs
7.3.2 Lookup Palette
7.3.3 Temporal Modulated Energy Distribution (TMED) Dithering
Page
7.3.4 Output FIFOs
7.3.5 LCD Controller Pin Usage
7.3.5.1 Passive Display Timing
7.3.5.2 Active Display Timing
7.3.5.3 Pixel Data Pins (L_DDx)
7.3.6 DMA
7.4 LCD External Palette and Frame Buffers
7.4.1 External Palette Buffer
7.4.2 External Frame Buffer
7-12 Intel PXA255 Processor Developers Manual
Figure 7-7. 2 Bits Per Pixel Data Memory Organization
Figure 7-8. 4 Bits Per Pixel Data Memory Organization
Figure 7-9. 8 Bits Per Pixel Data Memory Organization
Page
7.5 Functional Timing
Fram eBuf ferSize
--------------------------------------------------------------------------=
Intel PXA255 Processor Developers Manual 7-15
Figure 7-12. Passive Mode Start-of-Frame Timing
BLW = 0 BLW = 0 ELW = 0 ELW = 0
PPL = 319
Line 239 Data Line 0 Data
ELW = 0 ELW = 0 BLW = 0 BLW = 0
Figure 7-14. Passive Mode Pixel Clock and Data Pin Timing
Figure 7-15. Active Mode Timing
L_FCLK L_LCLK L_PCLK LDD[3:0]
7.6 Register Descriptions
7.6.1 LCD Controller Control Register 0 (LCCR0)
Page
Page
Page
7-22 Intel PXA255 Processor Developers Manual
Color Dual Passive
Top L_DD[7:0] Bottom L_DD[15:8] Color Single Active Whole L_DD[15:0]
Table 7-2. LCD Controller Data Pin Utilization (Sheet 2 of 2)
Color/Monochrome Panel
Passive Color Dual-Panel Display Pixel Ordering
Passive Color Single-Panel Display Pixel Ordering
Single/ Dual Panel
Page
7-24 Intel PXA255 Processor Developers Manual
7.6.2 LCD Controller Control Register 1 (LCCR1)
Table 7-3. LCCR0 Bit Definitions (Sheet 2 of 2)
Page
7.6.3 LCD Controller Control Register 2 (LCCR2)
7.6.4 LCD Controller Control Register 3 (LCCR3)
Page
Intel PXA255 Processor Developers Manual 7-31
where
LCLK = LCD/Memory Clock PCD = LCCR3[7:0]
PixelClock LCLK 2PCD 1+()
------------------------------= PCD LCLK 2PixelClock()
------------------------------------- 1=
7.6.5 LCD Controller DMA
7.6.5.1 Frame Descriptors
7.6.5.2 LCD DMA Frame Descriptor Address Registers (FDADRx)
7.6.5.3 LCD DMA Frame Source Address Registers (FSADRx)
7.6.5.4 LCD DMA Frame ID Registers (FIDRx)
7.6.5.5 LCD DMA Command Registers (LDCMDx)
7-36 Intel PXA255 Processor Developers Manual
Table 7-10. LDCMDx Bit Definitions
7.6.6 LCD DMA Frame Branch Registers (FBRx)
7.6.7 LCD Controller Status Register (LCSR)
Page
7-40 Intel PXA255 Processor Developers Manual
Table 7-12. LCSR Bit Definitions (Sheet 1 of 2)
7.6.8 LCD Controller Interrupt ID Register (LIIDR)
7.6.9 TMED RGB Seed Register (TRGBR)
7.6.10 TMED Control Register (TCR)
7-44 Intel PXA255 Processor Developers Manual
7.7 LCD Controller Register Summary
Table 7-15. TCR Bit Definitions
Table 7-16. LCD Controller Register Summary (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 7-45
Table 7-16. LCD Controller Register Summary (Sheet 2 of 2)
Page
Synchronous Serial Port Controller 8
8.1 Overview
8.2 Signal Description
8.2.1 External Interface to Synchronous Serial Peripherals
8.3 Functional Description
8.3.1 Data Transfer
8.4 Data Formats
8.4.1 Serial Data Formats for Transfer to/from Peripherals
8.4.1.2 SPI Format Details
8.4.1.3 Microwire Format Details
8.4.2 Parallel Data Formats for FIFO Storage
8.5 FIFO Operation and Data Transfers
8.5.1 Using Programmed I/O Data Transfers
8.5.2 Using DMA Data Transfers
8.6 Baud-Rate Generation
8.7 SSP Serial Port Registers
8.7.1 SSP Control Register 0 (SSCR0)
Intel PXA255 Processor Developers Manual 8-9
Synchronous Serial Port Controller
8.7.1.1 Data Size Select (DSS)
Table 8-2. SSCR0 Bit Definitions
8.7.1.2 Frame Format (FRF)
8.7.1.3 External Clock Select (ECS)
8.7.1.4 Synchronous Serial Port Enable (SSE)
8.7.1.5 Serial Clock Rate (SCR)
8.7.2 SSP Control Register 1 (SSCR1)
8.7.2.1 Receive FIFO Interrupt Enable (RIE)
8.7.2.2 Transmit FIFO Interrupt Enable (TIE)
8.7.2.3 Loop Back Mode (LBM)
8.7.2.4 Serial Clock Polarity (SPO)
8.7.2.5 Serial Clock Phase (SPH)
8.7.2.6 Microwire Transmit Data Size (MWDS)
8.7.2.7 Transmit FIFO Interrupt/DMA Threshold (TFT)
8.7.2.8 Receive FIFO Interrupt/DMA Threshold (RFT)
8.7.3 SSP Data Register (SSDR)
8.7.4 SSP Status Register (SSSR)
Intel PXA255 Processor Developers Manual 8-17
Synchronous Serial Port Controller
8.7.4.1 Transmit FIFO Not Full Flag (TNF)
Table 8-6. SSSR Bit Definitions
8.7.4.2 Receive FIFO Not Empty Flag (RNE)
8.7.4.3 SSP Busy Flag (BSY)
8.7.4.4 Transmit FIFO Service Request Flag (TFS)
8.7.4.5 Receive FIFO Service Request Flag (RFS)
8.7.4.6 Receiver Overrun Status (ROR)
8.8 SSP Controller Register Summary
Page
I2C Bus Interface Unit 9
9.1 Overview
9.2 Signal Description
9.3 Functional Description
Page
9.3.1 Operational Blocks
9.3.2 I2C Bus Interface Modes
9.3.3 Start and Stop Bus States
9.3.3.1 START Condition
9.3.3.2 No START or STOP Condition
9.3.3.3 STOP Condition
9-6 Intel PXA255 Processor Developers Manual
Figure 9-3. START and STOP Conditions
9.4 I2C Bus Operation
9.4.1 Serial Clock Line (SCL) Generation
9.4.2 Data and Addressing Management
9.4.2.1 Addressing a Slave Device
9.4.3 I2C Acknowledge
9.4.4 Polling
9.4.5 Arbitration
9.4.5.1 SCL Arbitration
9.4.5.2 SDA Arbitration
9-12 Intel PXA255 Processor Developers Manual
9.4.6 Master Operations
Intel PXA255 Processor Developers Manual 9-13
Table 9-5. Master Transactions (Sheet 2 of 2)
9.4.7 Slave Operations
Intel PXA255 Processor Developers Manual 9-15
Table 9-6. Slave Transactions
9.4.8 General Call Address
9.5 Slave Mode Programming Examples
9.5.1 Initialize Unit
9.5.2 Write n Bytes as a Slave
9.5.3 Read n Bytes as a Slave
9.6 Master Programming Examples
9.6.1 Initialize Unit
9.6.2 Write 1 Byte as a Master
9.6.3 Read 1 Byte as a Master
9.6.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master
9.6.5 Read 2 Bytes as a Master - Send STOP Using the Abort
9.7 Glitch Suppression Logic
9.8 Reset Conditions
9.9 Register Definitions
9.9.1 I2C Bus Monitor Register (IBMR)
9.9.2 I2C Data Buffer Register (IDBR)
Intel PXA255 Processor Developers Manual 9-23
9.9.3 I2C Control Register (ICR)
The processor uses the ICR, shown in Table 9-10, to control the I2C unit.
Table 9-9. IDBR Bit Definitions
Table 9-10. ICR Bit Definitions (Sheet 1 of 3)
9-24 Intel PXA255 Processor Developers Manual
Table 9-10. ICR Bit Definitions (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 9-25
9.9.4 I2C Status Register (ISR)
This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.
Table 9-10. ICR Bit Definitions (Sheet 3 of 3)
9-26 Intel PXA255 Processor Developers Manual
Table 9-11. ISR Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 9-27
9.9.5 I2C Slave Address Register (ISAR)
Table 9-11. ISR Bit Definitions (Sheet 2 of 2)
Table 9-12. ISAR Bit Definitions
Page
UARTs 10
10.1 Feature List
10.2 Overview
10.2.1 Full Function UART
10.2.2 Bluetooth UART
10.2.3 Standard UART
10.2.4 Compatibility with 16550
10.3 Signal Descriptions
10-4 Intel PXA255 Processor Developers Manual
10.4 UART Operational Description
The format of a UART data frame is shown in Figure 10-1.
Table 10-1. UART Signal Descriptions (Sheet 2 of 2)
Figure 10-1. Example UART Data Frame
10.4.1 Reset
10.4.2 Internal Register Descriptions
10.4.2.1 Receive Buffer Register (RBR)
10.4.2.2 Transmit Holding Register (THR)
10.4.2.3 Divisor Latch Registers (DLL and DLH)
----------------------------------=
BaudRate 14.7456 MHz 16xDivisor()
10.4.2.4 Interrupt Enable Register (IER)
Intel PXA255 Processor Developers Manual 10-9
10.4.2.5 Interrupt Identification Register (IIR)
Table 10-7. IER Bit Definitions
Page
Intel PXA255 Processor Developers Manual 10-11
Table 10-10. Interrupt Identification Register Decode (Sheet 1 of 2)
Table 10-9. IIR Bit Definitions (Sheet 2 of 2)
10-12 Intel PXA255 Processor Developers Manual
10.4.2.6 FIFO Control Register (FCR)
Table 10-10. Interrupt Identification Register Decode (Sheet 2 of 2)
Table 10-11. FCR Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 10-13
10.4.2.7 Line Control Register (LCR)
Table 10-11. FCR Bit Definitions (Sheet 2 of 2)
10-14 Intel PXA255 Processor Developers Manual
Table 10-12. LCR Bit Definitions
10.4.2.8 Line Status Register (LSR)
10-16 Intel PXA255 Processor Developers Manual
Table 10-13. LSR Bit Definitions (Sheet 2 of 3)
Intel PXA255 Processor Developers Manual 10-17
Table 10-13. LSR Bit Definitions (Sheet 3 of 3)
10-18 Intel PXA255 Processor Developers Manual
10.4.2.9 Modem Control Register (MCR)
Table 10-14. MCR Bit Definitions (Sheet 1 of 2)
10.4.2.10 Modem Status Register (MSR)
10-20 Intel PXA255 Processor Developers Manual
Table 10-15. MSR Bit Definitions
10.4.2.11 Scratchpad Register (SPR)
10.4.3 FIFO Interrupt Mode Operation
10.4.3.1 Receive Interrupt
10.4.3.2 Character Timeout Indication Interrupt
10.4.3.3 Transmit Interrupt
10.4.4 FIFO Polled Mode Operation
10.4.5 DMA Requests
10.4.5.1 Trailing Bytes in the Receive FIFO
10.4.6 Slow Infrared Asynchronous Interface
10.4.6.1 Infrared Selection Register (ISR)
10-24 Intel PXA255 Processor Developers Manual
10.4.6.2 Operation
Table 10-17. ISR Bit Definitions
Page
10.5 UART Register Summary
Intel PXA255 Processor Developers Manual 10-27
Table 10-20. STUART Register Summary
Table 10-19. BTUART Register Summary (Sheet 2 of 2)
10.5.1 UART Register Differences
Fast Infrared Communication Port 11
11.1 Signal Description
11.2 FICP Operation
11.2.1 4PPM Modulation
11.2.2 Frame Format
11.2.3 Address Field
11.2.4 Control Field
11.2.5 Data Field
11.2.6 CRC Field
11.2.7 Baud Rate Generation
11.2.8 Receive Operation
11.2.9 Transmit Operation
11.2.10 Transmit and Receive FIFOs
11.2.11 Trailing or Error Bytes in the Receive FIFO
11.3 FICP Register Definitions
11-8 Intel PXA255 Processor Developers Manual
11.3.1 FICP Control Register 0 (ICCR0)
Table 11-2. ICCR0 Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 11-9
Table 11-2. ICCR0 Bit Definitions (Sheet 2 of 2)
11.3.2 FICP Control Register 1 (ICCR1)
Intel PXA255 Processor Developers Manual 11-11
11.3.3 FICP Control Register 2 (ICCR2)
Table 11-4. ICCR2 Bit Definitions
11.3.4 FICP Data Register (ICDR)
11.3.5 FICP Status Register 0 (ICSR0)
11-14 Intel PXA255 Processor Developers Manual
Table 11-6. ICSR0 Bit Definitions (Sheet 2 of 2)
Intel PXA255 Processor Developers Manual 11-15
11.3.6 FICP Status Register 1 (ICSR1)
Table 11-7. ICSR1 Bit Definitions
11.4 FICP Register Summary
USB Device Controller 12
12.1 USB Overview
12.2 Device Configuration
12.3 USB Protocol
12.3.1 Signalling Levels
12.3.2 Bit Encoding
12.3.3 Field Formats
12.3.4 Packet Formats
12.3.4.1 Token Packet Type
12.3.4.2 Start of Frame Packet Type
12.3.4.3 Data Packet Type
12.3.4.4 Handshake Packet Type
12.3.5 Transaction Formats
12.3.5.1 Bulk Transaction Type
12.3.5.2 Isochronous Transaction Type
12.3.5.3 Control Transaction Type
12.3.5.4 Interrupt Transaction Type
12.3.6 UDC Device Requests
12.3.7 Configuration
12.4 UDC Hardware Connection
12.4.1 Self-Powered Device
12.4.1.1 When GPIOn and GPIOx are Different Pins
12.4.1.2 When GPIOn and GPIOx are the Same Pin
12.4.2 Bus-Powered Devices
12.5 UDC Operation
12.5.1 Case 1: EP0 Control Read
12.5.2 Case 2: EP0 Control Read with a Premature Status Stage
12.5.3 Case 3: EP0 Control Write With or Without a Premature Status Stage
12.5.4 Case 4: EP0 No Data Command
12.5.5 Case 5: EP1 Data Transmit (BULK-IN)
12.5.5.1 Software Enables the DMA
12.5.5.2 Software Enables the EP1 Interrupt
12.5.6 Case 6: EP2 Data Receive (BULK-OUT)
12.5.6.1 Software Enables the DMA
12.5.6.2 Software Allows the Megacell to Handle the Transaction
12.5.7 Case 7: EP3 Data Transmit (ISOCHRONOUS-IN)
12.5.7.1 Software Enables DMA
12.5.7.2 Software Enables the EP3 Interrupt
12.5.7.3 Software Enables the SOF Interrupt
12.5.8 Case 8: EP4 Data Receive (ISOCHRONOUS-OUT)
12.5.8.1 Software Enables the DMA
12.5.8.2 Software Allows the Megacell to Handle the Transaction
12.5.8.3 Software Enables the SOF Interrupt
12.5.9 Case 9: EP5 Data Transmit (INTERRUPT-IN)
12.5.10 Case 10: RESET Interrupt
12.5.11 Case 11: SUSPEND Interrupt
12.5.12 Case 12: RESUME Interrupt
12.6 UDC Register Definitions
12.6.1 UDC Control Register (UDCCR)
12.6.1.1 UDC Enable (UDE)
Page
12.6.2 UDC Control Function Register (UDCCFR)
12.6.2.1 ACK Control Mode
12.6.2.2 ACK Response Enable
12.6.3 UDC Endpoint 0 Control/Status Register (UDCCS0)
12.6.3.1 OUT Packet Ready (OPR)
12.6.3.2 IN Packet Ready (IPR)
12.6.3.3 Flush Tx FIFO (FTF)
12.6.3.4 Device Remote Wakeup Feature (DRWF)
12.6.3.5 Sent Stall (SST)
12.6.3.6 Force Stall (FST)
12.6.3.7 Receive FIFO Not Empty (RNE)
12.6.4 UDC Endpoint x Control/Status Register (UDCCS1/6/11)
12.6.4.1 Transmit FIFO Service (TFS)
Table 12-15. UDCCS1/6/11 Bit Definitions
12.6.4.2 Transmit Packet Complete (TPC)
12.6.4.3 Flush Tx FIFO (FTF)
12.6.4.4 Transmit Underrun (TUR)
12.6.4.5 Sent STALL (SST)
12.6.4.6 Force STALL (FST)
12.6.5 UDC Endpoint x Control/Status Register (UDCCS2/7/12)
12.6.5.1 Receive FIFO Service (RFS)
12.6.5.2 Receive Packet Complete (RPC)
12.6.5.3 Bit 2 Reserved
12.6.5.4 DMA Enable (DME)
12.6.5.5 Sent Stall (SST)
12.6.6 UDC Endpoint x Control/Status Register (UDCCS3/8/13)
12.6.6.1 Transmit FIFO Service (TFS)
12.6.6.2 Transmit Packet Complete (TPC)
12.6.6.3 Flush Tx FIFO (FTF)
12.6.6.4 Transmit Underrun (TUR)
12.6.7 UDC Endpoint x Control/Status Register (UDCCS4/9/14)
12.6.7.1 Receive FIFO Service (RFS)
12.6.7.2 Receive Packet Complete (RPC)
12.6.7.3 Receive Overflow (ROF)
12.6.7.4 DMA Enable (DME)
12.6.7.5 Bits 5:4 Reserved
12.6.8 UDC Endpoint x Control/Status Register (UDCCS5/10/15)
12.6.8.1 Transmit FIFO Service (TFS)
12.6.8.2 Transmit Packet Complete (TPC)
12.6.8.3 Flush Tx FIFO (FTF)
12.6.8.4 Transmit Underrun (TUR)
12.6.8.5 Sent STALL (SST)
12.6.9 UDC Interrupt Control Register 0 (UICR0)
Intel PXA255 Processor Developers Manual 12-37
12.6.9.1 Interrupt Mask Endpoint x (IMx), Where x is 0 through 7
Table 12-20. UICR0 Bit Definitions
12.6.10 UDC Interrupt Control Register 1 (UICR1)
12.6.10.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15.
12.6.11 UDC Status/Interrupt Register 0 (USIR0)
12.6.11.1 Endpoint 0 Interrupt Request (IR0)
12.6.11.2 Endpoint 1 Interrupt Request (IR1)
Page
12.6.12 UDC Status/Interrupt Register 1 (USIR1)
12.6.12.1 Endpoint 8 Interrupt Request (IR8)
12.6.12.2 Endpoint 9 Interrupt Request (IR9)
12.6.12.3 Endpoint 10 Interrupt Request (IR10)
12.6.13 UDC Frame Number High Register (UFNHR)
12.6.13.1 UDC Frame Number MSB (FNMSB)
12.6.13.2 Isochronous Packet Error Endpoint 4 (IPE4)
12.6.13.3 Isochronous Packet Error Endpoint 9 (IPE9)
12.6.13.4 Isochronous Packet Error Endpoint 14 (IPE14)
12.6.13.5 Start of Frame Interrupt Mask (SIM)
12.6.14 UDC Frame Number Low Register (UFNLR)
12.6.15 UDC Byte Count Register x (UBCR2/4/7/9/12/14)
12.6.15.1 Endpoint x Byte Count (BC)
12.6.16 UDC Endpoint 0 Data Register (UDDR0)
12.6.17 UDC Endpoint x Data Register (UDDR1/6/11)
12.6.18 UDC Endpoint x Data Register (UDDR2/7/12)
12.6.19 UDC Endpoint x Data Register (UDDR3/8/13)
12.6.20 UDC Endpoint x Data Register (UDDR4/9/14)
12.6.21 UDC Endpoint x Data Register (UDDR5/10/15)
12.7 USB Device Controller Register Summary
Intel PXA255 Processor Developers Manual 12-49
Table 12-33. USB Device Controller Register Summary (Sheet 2 of 3)
Page
AC97 Controller Unit 13
13.1 Overview
13.2 Feature List
13.3 Signal Description
13.3.1 Signal Configuration Steps
13.3.2 Example AC-link
13.4 AC-link Digital Serial Interface Protocol
13.4.1 AC-link Audio Output Frame (SDATA_OUT)
Page
13.4.1.1 Slot 0: Tag Phase
13.4.1.2 Slot 1: Command Address Port
13.4.1.3 Slot 2: Command Data Port
13.4.1.4 Slot 3: PCM Playback Left Channel
13.4.1.5 Slot 4: PCM Playback Right Channel
13.4.1.6 Slot 5: Modem Line CODEC
13.4.1.7 Slots 6-11: Reserved
13.4.2 AC-link Audio Input Frame (SDATA_IN)
13.4.2.1 Slot 0: Tag Phase
SYNC SDATA_IN
BIT_CLK
13.4.2.2 Slot 1: Status Address Port/SLOTREQ bits
13.4.2.3 Slot 2: Status Data Port
13.4.2.4 Slot 3: PCM Record Left Channel
13.4.2.5 Slot 4: PCM Record Right Channel
13.4.2.6 Slot 5: Optional Modem Line CODEC
13.4.2.7 Slot 6: Optional Dedicated Microphone Record Data
13.5 AC-link Low Power Mode
13.5.1 Powering Down the AC-link
SYNC BITCLK
SDATA_IN
13.5.2 Waking up the AC-link
13.5.2.1 Wake up triggered by the CODEC
13.5.2.2 Wake Up Triggered by the ACUNIT
13.6 ACUNIT Operation
13.6.1 Initialization
Page
13.6.2 Trailing bytes
13.6.3 Operational Flow for Accessing CODEC Registers
13.7 Clocks and Sampling Frequencies
13.8 Functional Description
13.8.1 FIFOs
13.8.2 Interrupts
13.8.3 Registers
13.8.3.1 Global Control Register (GCR)
Intel PXA255 Processor Developers Manual 13-21
13.8.3.2 Global Status Register (GSR)
Table 13-7. GCR Bit Definitions (Sheet 2 of 2)
13-22 Intel PXA255 Processor Developers Manual
Table 13-8. GSR Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 13-23
13.8.3.3 PCM-Out Control Register (POCR)
Table 13-8. GSR Bit Definitions (Sheet 2 of 2)
Table 13-9. POCR Bit Definitions (Sheet 1 of 2)
13-24 Intel PXA255 Processor Developers Manual
13.8.3.4 PCM-In Control Register (PICR)
Table 13-9. POCR Bit Definitions (Sheet 2 of 2)
Table 13-10. PICR Bit Definitions
Intel PXA255 Processor Developers Manual 13-25
13.8.3.5 PCM-Out Status Register (POSR)
13.8.3.6 PCM_In Status Register (PISR)
Table 13-11. POSR Bit Definitions
Table 13-12. PISR Bit Definitions
13.8.3.7 CODEC Access Register (CAR)
13.8.3.8 PCM Data Register (PCDR)
13.8.3.9 Mic-In Control Register (MCCR)
13.8.3.10 Mic-In Status Register (MCSR)
13-28 Intel PXA255 Processor Developers Manual
13.8.3.11 Mic-In Data Register (MCDR)
Table 13-16. MCSR Bit Definitions
Table 13-17. MCDR Bit Definitions
Intel PXA255 Processor Developers Manual 13-29
13.8.3.12 Modem-Out Control Register (MOCR)
13.8.3.13 Modem-In Control Register (MICR)
Figure 13-10. Mic-in Receive-Only Operation
Table 13-18. MOCR Bit Definitions
13-30 Intel PXA255 Processor Developers Manual
13.8.3.14 Modem-Out Status Register (MOSR)
13.8.3.15 Modem-In Status Register (MISR)
Table 13-19. MICR Bit Definitions
Table 13-20. MOSR Bit Definitions
Intel PXA255 Processor Developers Manual 13-31
13.8.3.16 Modem Data Register (MODR)
Table 13-21. MISR Bit Definitions
Table 13-22. MODR Bit Definitions
13.8.3.17 Accessing CODEC Registers
Intel PXA255 Processor Developers Manual 13-33
Table 13-23. Address Mapping for CODEC Registers (Sheet 1 of 2)
13-34 Intel PXA255 Processor Developers Manual
Table 13-23. Address Mapping for CODEC Registers (Sheet 2 of 2)
Intel PXA255 Processor Developers Manual 13-35
13.9 AC97 Register Summary
Page
Inter-Integrated-Circuit Sound (I2S) Controller 14
14.1 Overview
14.2 Signal Descriptions
14.3 Controller Operation
14.3.1 Initialization
14.3.2 Disabling and Enabling Audio Replay
14.3.3 Disabling and Enabling Audio Record
14.3.4 Transmit FIFO Errors
14.3.5 Receive FIFO Errors
14.3.6 Trailing Bytes
14.4 Serial Audio Clocks and Sampling Frequencies
14.5 Data Formats
14.5.1 FIFO and Memory Format
14.5.2 I2S and MSB-Justified Serial Audio Formats
Page
14.6 Registers
14.6.1 Serial Audio Controller Global Control Register (SACR0)
Intel PXA255 Processor Developers Manual 14-9
14.6.1.1 Special purpose FIFO Read/Write function
Table 14-3. SACR0 Bit Definitions
14.6.1.2 Suggested TFTH and RFTH for DMA servicing
14.6.2 Seri al Audio C ontroller I (SACR1)
Intel PXA255 Processor Developers Manual 14-11
14.6.3 Serial Audio Controller I2S/MSB-Justified Status Register (SASR0)
Table 14-6. SACR1 Bit Definitions
14-12 Intel PXA255 Processor Developers Manual
14.6.4 Serial Audio Clock Divider Register (SADIV)
Table 14-7. SASR0 Bit Definitions
14.6.5 Serial Audio Interrupt Clear Register (SAICR)
14.6.6 Serial Audio Interrupt Mask Register (SAIMR)
14.6.7 Serial Audio Data Register (SADR)
14.7 Interrupts
14.8 I2S Controller Register Summary
14-16 Intel PXA255 Processor Developers Manual
Table 14-12. Register Memory Map
MultiMediaCard Controller 15
15.1 Overview
Page
Page
15.2 MMC Controller Functional Description
Page
15.2.1 Signal Description
15.2.2 MMC Controller Reset
15.2.3 Card Initialization Sequence
15.2.4 MMC and SPI Modes
15.2.4.1 MMC Mode
15.2.4.2 SPI Mode
15.2.5 Error Detection
15.2.6 Interrupts
15.2.7 Clock Control
15.2.8 Data FIFOs
15.2.8.1 Response Data FIFO (MMC_RES)
15.2.8.2 Receive Data FIFO, MMC_RXFIFO
15.2.8.3 Transmit Data FIFO, MMC_TXFIFO
15.2.8.4 DMA and Program I/O
15.3 Card Communication Protocol
15.3.1 Basic, No Data, Command and Response Sequence
15.3.2 Data Transfer
15.3.2.1 Block Data Write
15.3.2.2 Block Data Read
15.3.2.3 Stream Data Write
15.3.3 Busy Sequence
15.3.4 SPI Functionality
15.4 MultiMediaCard Controller Operation
15.4.1 Start and Stop Clock
15.4.2 Initialize
15.4.3 Enabling SPI Mode
15.4.4 No Data Command and Response Sequence
15.4.5 Erase
15.4.6 Single Data Block Write
15.4.7 Single Block Read
15.4.8 Multiple Block Write
15.4.9 Multiple Block Read
15.4.10 Stream Write
15.4.11 Stream Read
15.5 MMC Controller Registers
15.5.1 MMC_STRPCL Register
Intel PXA255 Processor Developers Manual 15-23
15.5.2 MMC_Status Register (MMC_STAT)
Table 15-5. MMC_STRPCL Bit Definitions
Table 15-6. MMC_STAT Bit Definitions (Sheet 1 of 2)
15-24 Intel PXA255 Processor Developers Manual
15.5.3 MMC_CLKRT Register (MMC_CLKRT)
Table 15-6. MMC_STAT Bit Definitions (Sheet 2 of 2)
Intel PXA255 Processor Developers Manual 15-25
15.5.4 MMC_SPI Register (MMC_SPI)
MMC_SPI, shown in Table 15-8, is for SPI mode only and is set by the software.
Table 15-7. MMC_CLK Bit Definitions
Table 15-8. MMC_SPI Bit Definitions (Sheet 1 of 2)
15-26 Intel PXA255 Processor Developers Manual
15.5.5 MMC_CMDAT Register (MMC_CMDAT)
Table 15-8. MMC_SPI Bit Definitions (Sheet 2 of 2)
Table 15-9. MMC_CMDAT Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 15-27
15.5.6 MMC_RESTO Register (MMC_RESTO)
Table 15-9. MMC_CMDAT Bit Definitions (Sheet 2 of 2)
Table 15-10. MMC_RESTO Bit Definitions
15.5.7 MMC_RDTO Register (MMC_RDTO)
15.5.8 MMC_BLKLEN Register (MMC_BLKLEN)
15.5.9 MMC_NOB Register (MMC_NOB)
15-30 Intel PXA255 Processor Developers Manual
15.5.10 MMC_PRTBUF Register (MMC_PRTBUF)
15.5.11 MMC_I_MASK Register (MMC_I_MASK)
MMC_I_MASK, shown in Table 15-15, masks off the various interrupts when set to a 1.
Table 15-14. MMC_PRTBUF Bit Definitions
Table 15-15. MMC_I_MASK Bit Definitions (Sheet 1 of 2)
15.5.12 MMC_I_REG Register (MMC_I_REG)
Table 15-15. MMC_I_MASK Bit Definitions (Sheet 2 of 2)
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Table 15-16. MMC_I_REG Bit Definitions
Intel PXA255 Processor Developers Manual 15-33
15.5.13 MMC_CMD Register (MMC_CMD)
MMC_CMD, shown in Table 15-17, specifies the command number.
Table 15-17. MMC_CMD Register
Table 15-18. Command Index Values (Sheet 1 of 3)
15-34 Intel PXA255 Processor Developers Manual
Table 15-18. Command Index Values (Sheet 2 of 3)
15.5.14 MMC_ARGH Register (MMC_ARGH)
15.5.15 MMC_ARGL Register (MMC_ARGL)
15.5.16 MMC_RES FIFO
15.5.17 MMC_RXFIFO FIFO
15.5.18 MMC_TXFIFO FIFO
15.6 MultiMediaCard Controller Register Summary
Page
Network SSP Serial Port 16
16.1 Overview
16.2 Features
16.3 Signal Description
16.4 Operation
16.4.1 Processor and DMA FIFO Access
16.4.2 Trailing Bytes in the Receive FIFO
16.4.2.1 Time-out
16.4.2.2 Removing Trailing Bytes
16.4.3 Data Formats
Page
16.4.3.1 TI Synchronous Serial Protocol* Details
16.4.3.2 SPI Protocol Details
Page
Page
16.4.3.3 Microwire* Protocol Details
16.4.3.4 PSP Details
Page
16-12 Intel PXA255 Processor Developers Manual
Figure 16-10. Programmable Serial Protocol (single transfers)
Table 16-2. Programmable Serial Protocol (PSP) Parameters
16.4.4 Hi-Z on SSPTXD
16.4.4.1 TI Synchronous Serial Port
16.4.4.2 Motorola SPI
16.4.4.3 National Semiconductor Microwire
16.4.4.4 Programmable Serial Protocol
16-16 Intel PXA255 Processor Developers Manual
Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame)
Figure 16-17. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame)
16.4.5 FIFO Operation
16.4.6 Baud-Rate Generation
16.5 Register Descriptions
16.5.1 SSP Control Register 0 (SSCR0)
Intel PXA255 Processor Developers Manual 16-19
Table 16-3. SSCR0 Bit Definitions (Sheet 1 of 2)
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16.5.2 SSP Control Register 1 (SSCR1)
Table 16-3. SSCR0 Bit Definitions (Sheet 2 of 2)
Intel PXA255 Processor Developers Manual 16-21
Table 16-4. SSCR1 Bit Definitions (Sheet 1 of 2)
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16.5.3 SSP Programmable Serial Protocol Register (SSPSP)
Table 16-4. SSCR1 Bit Definitions (Sheet 2 of 2)
Intel PXA255 Processor Developers Manual 16-23
Table 16-5. SSPSP Bit Definitions (Sheet 1 of 2)
16.5.4 SSP Time Out Register (SSTO)
16.5.5 SSP Interrupt Test Register (SSITR)
16.5.6 SSP Status Register (SSSR)
16-26 Intel PXA255 Processor Developers Manual
Table 16-8. SSSR Bit Definitions (Sheet 1 of 3)
Intel PXA255 Processor Developers Manual 16-27
Table 16-8. SSSR Bit Definitions (Sheet 2 of 3)
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16.5.7 SSP Data Register (SSDR)
Table 16-8. SSSR Bit Definitions (Sheet 3 of 3)
16.6 Network SSP Serial Port Register Summary
Page
Hardware UART 17
17.1 Overview
17.2 Features
Page
Intel PXA255 Processor Developers Manual 17-3
17.3 Signal Descriptions
The format of a UART data frame is shown in Figure 17-1.
17.4 Operation
Table 17-1. UART Signal Descriptions
Figure 17-1. Example UART Data Frame
17.4.1 Reset
17.4.2 FIFO Operation
17.4.2.1 FIFO Interrupt Mode Operation
17.4.2.2 FIFO Polled Mode Operation
17.4.2.3 FIFO DMA Mode Operation
17.4.2.4 DMA Receive Programming Errors
17.4.2.5 DMA Error Handling
17.4.2.6 Removing Trailing Bytes In DMA Mode
17.4.3 Autoflow Control
17.4.4 Auto-Baud-Rate Detection
17.4.5 Slow Infrared Asynchronous Interface
17.4.5.1 Operation
Page
17.5 Register Descriptions
17.5.1 Receive Buffer Register (RBR)
17.5.2 Transmit Holding Register (THR)
17.5.3 Divisor Latch Registers (DLL and DLH)
17.5.4 Interrupt Enable Register (IER)
BaudRate 14.7456 MHz 16xDivisor()
----------------------------------=
17-12 Intel PXA255 Processor Developers Manual
Table 17-6. IER Bit Definitions
17.5.5 Interrupt Identification Register (IIR)
17-14 Intel PXA255 Processor Developers Manual
Table 17-8. IIR Bit Definitions (Sheet 2 of 2)
Table 17-9. Interrupt Identification Register Decode (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 17-15
17.5.6 FIFO Control Register (FCR)
Table 17-9. Interrupt Identification Register Decode (Sheet 2 of 2)
Table 17-10. FCR Bit Definitions (Sheet 1 of 2)
17-16 Intel PXA255 Processor Developers Manual
17.5.7 Receive FIFO Occupancy Register (FOR)
Table 17-10. FCR Bit Definitions (Sheet 2 of 2)
Table 17-11. FOR Bit Definitions
17.5.8 Auto-Baud Control Register (ABR)
17.5.9 Auto-Baud Count Register (ACR)
17-18 Intel PXA255 Processor Developers Manual
17.5.10 Line Control Register (LCR)
Table 17-13. ACR Bit Definitions
Table 17-14. LCR Bit Definitions (Sheet 1 of 2)
17.5.11 Line Status Register (LSR)
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Table 17-15. LSR Bit Definitions (Sheet 1 of 2)
Intel PXA255 Processor Developers Manual 17-21
17.5.12 Modem Control Register (MCR)
Table 17-15. LSR Bit Definitions (Sheet 2 of 2)
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Table 17-16. MCR Bit Definitions (Sheet 1 of 2)
17.5.13 Modem Status Register (MSR)
17.5.14 Scratchpad Register (SCR)
17.5.15 Infrared Selection Register (ISR)
Intel PXA255 Processor Developers Manual 17-25
17.6 Hardware UART Register Summary
Table 17-20 contains the register addresses for the HWUART.
Table 17-19. ISR Bit Definitions
Table 17-20. HWUART Register Locations (Sheet 1 of 2)
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Table 17-20. HWUART Register Locations (Sheet 2 of 2)