Intel PXA255 manual Asynchronous Static Memory Control Registers MSCx

Memory Controller

6.7.3Asynchronous Static Memory Control Registers (MSCx)

The MSCx, shown in Table 6-24, are read/write registers and contain control bits for configuring Static Memory (or Variable Latency I/O) that correspond to chip-select pairs nCS(1:0), nCS(3:2), and nCS(5:4), respectively. Timing fields are specified as numbers of memory clock cycles. Each of the three registers contain two identical CNFG fields One for each chip select in the pair.

When programming a different memory type in an MSC register, ensure that the new value has been accepted and programmed before issuing a command to that memory. To do this, the MSC register must be read after it is written and before an access to the memory is attempted. This is especially important when changing from ROM/Flash to an unconstrained writable memory type (such as SRAM).

If any of the nCS[3:0] banks is configured for Synchronous Static Memory via SXCNFG[SXENx], the corresponding half-words of MSC0 and/or MSC1 are ignored, except MSCx:RBWx, the data width. Another exception is non-SDRAM timing Synchronous Flash, which writes asynchronously and requires these programmed values.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

6-46 Intel® PXA255 Processor Developer’s Manual