Memory Controller

6.7.6.1Variable Latency I/O Timing Diagrams and Parameters

Figure 6-21shows the timing for Variable Latency I/O reads and Figure 6-22shows the timing for Variable Latency I/O writes.

Figure 6-21. 32-Bit Variable Latency I/O Read Timing (Burst-of-Four, One Wait Cycle Per Beat) (MSC0[RDF] = 2, MSC0[RDN] = 2, MSC0[RRR] = 1)

0ns

CLK_MEM nCS[0]

tAS

MA[25:2]

addr

MA[1:0]

0 Waits

100ns

addr + 1

RDN+2

1 Wait

200ns

addr + 2

"00"

RDN+2

2 Waits

300ns

addr + 3

RDN+2

3 Waits

nOE nPWE RDnWR

RDY RDY_sync

RDF+1+WaitsRDF+1+Waits

RDF+1+Waits RRR*2+1

MD[31:0]

 

DQM[3:0]

"0000"

*MSC0: RDF0 = 3, RDN0 = 2, RRR0 = 1

tAS = Address Setup to nCS asserted = 1 clk_mem

 

tAH = Address Hold from nOE deasserted = 1 clk_mem

 

tASRW0 = Address Setup to nOE asserted (1st access) = 3 clk_mems

 

tASRWn = Address Setup to nOE asserted (next access(s)) = RDN clk_mems

 

tCES = nCS setup to nOE asserted = 2 clk_mems

 

tCEH = nCS hold from nOE deasserted = 1 clk_mem

 

tDSOH = MD setup to Address changing = 1.5 clk_mems plus

 

board routing delays

 

tDOH = MD hold from Address changing = 0 ns

 

tRDYH = RDY Hold from nOE deasserted = 0 ns

6-56

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Variable Latency I/O Timing Diagrams and Parameters, RDF+1+Waits RRR*2+1