AC-link Audio Output Frame | Intel PXA255 specification

AC’97 Controller Unit

Figure 13-3. AC-link Audio Output Frame

Tag Phase

20.8uS

Data Phase

(48 KHz)

SYNC

12.288 MHz

81.4 nS

BIT_CLK

SDATA_OUT

Valid

slot(1) slot(2)

slot(12) "0"

codec ID codec ID

19

0

19

0

19

0

19

0

Frame

End of previous

Time Slot "Valid"

Slot 1

Slot 2

Slot 3

Slot 12

Audio Frame

Bits

("1" = time slot contains valid PCM data)

A new audio output frame begins with a low-to-high SYNC transition synchronous to BITCLK’s rising edge. BITCLK’s falling edge immediately follows and AC’97 samples SYNC’s assertion. BITCLK’s falling edge marks the instance that AC-link’s sides are each aware that a new audio frame has started. On BITCLK’s next rising edge, the ACUNIT transitions SDATA_OUT into the slot 0’s first bit position (valid frame bit). Each new bit position is presented to AC-link on a BITCLK rising edge and then sampled by AC’97 on the following BITCLK falling edge. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned.

Figure 13-4. Start of Audio Output Frame

		AC '97 samples SYNC assertion here
	SYNC	AC '97 samples first SDATA_OUT bit of frame here
	BIT_CLK
	SDATA_OUT	Valid	slot(1) slot(2)
	SDATA_OUT	Frame	slot(1) slot(2)
		Frame

End of previous

Audio Frame

The SDATA_OUT composite stream is MSB-justified (MSB first). The ACUNIT fills all non-valid slot bit positions with zeroes. If fewer than 20 valid bits exist in an assigned valid time slot, the ACUNIT stuffs all trailing non-valid bit positions of the 20-bit slot with zeroes.

For example, if a 16-bit sample stream is being played to an AC’97 DAC, the first 16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the ACUNIT stuffs with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the implemented DAC’s resolution (16-, 18-, or 20-bit).

Note: When the ACUNIT transmits mono audio sample streams, software must ensure that the left and right sample stream time slots are filled with identical data.

Intel® PXA255 Processor Developer’s Manual

13-5

Image 457

Intel PXA255 manual AC-link Audio Output Frame

Contents

Intel PXA255 Processor Intel PXA255 Processor Developer’s Manual Contents Power Manager General Configuration Register Pcfr Contents Expansion Card Interface Timing Diagrams and Parameters DMA 10-1 11-1 12.6 14.3 15.5 Figures BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF = 10-25 Tables Clocks Manager Register Summary Sxcnfg 10-6 10-8 12-26 15-7 Date Revision Description Revision History Xxiv System Integration Features Intel XScale Microarchitecture Features Memory Controller Clocks and Power ControllersUniversal Serial Bus USB Client LCD Controller DMA Controller Dmac6 AC97 Controller Inter-IC Sound I2S Controller Inter-Integrated Circuit I2C Bus Interface Unit Synchronous Serial Protocol Controller SspcGpio UARTs Real-Time Clock RTC OS TimersPulse-Width Modulator PWM Interrupt Control Introduction Overview System Architecture Coprocessor 7 Register 4 Psfs Bit Intel XScale Microarchitecture Implementation Options CPU Core Fault Register Bit Definitions Coprocessor 14 Register 6 and 7- Clock and Power ManagementCoprocessor 14 Registers 0-3 Performance Monitoring Coprocessor 15 Register 0 ID Register Definition ID Bit Definitions Coprocessor 15 Register 1 P-BitPXA255 Processor ID Values ARM ID Jtag ID Semaphores I/O OrderingInterrupts Unit Sleep Mode Gpio Reset Watchdog Reset Hard Reset ResetUSB ICP Selecting Peripherals vs. General Purpose I/O Internal Registers Power Management Power on Reset and Boot OperationPin List Processor Pin Types Pin Name Type Signal Descriptions Reset State Sleep State Pin & Signal Descriptions for the PXA255 Processor Sheet 1 Pin & Signal Descriptions for the PXA255 Processor Sheet 2 Psktsel Pin & Signal Descriptions for the PXA255 Processor Sheet 3 Pin & Signal Descriptions for the PXA255 Processor Sheet 4 Pin & Signal Descriptions for the PXA255 Processor Sheet 5 Pin & Signal Descriptions for the PXA255 Processor Sheet 6 Pin & Signal Descriptions for the PXA255 Processor Sheet 7 Bootsel Pin & Signal Descriptions for the PXA255 Processor Sheet 8Rtcclk Icocz Pwren Pin Description Notes Sheet 1 Pin & Signal Descriptions for the PXA255 Processor Sheet 9 Pin Description Notes Sheet 2 Memory Map Memory Map Part One From 0x80000000 to 0xFFFF Ffff Memory Map Part Two From 0x00000000 to 0x7FFF Ffff System Architecture Register Summary Unit Address Register Symbol Register DescriptionSystem Architecture Register Address Summary Sheet 1 System Architecture Register Address Summary Sheet 2 System Architecture Register Address Summary Sheet 3 System Architecture Register Address Summary Sheet 4 Unit System Architecture Register Address Summary Sheet 5 System Architecture Register Address Summary Sheet 6 Unit Address System Architecture Register Address Summary Sheet 7 System Architecture Register Address Summary Sheet 8 System Architecture Register Address Summary Sheet 9 System Architecture Register Address Summary Sheet 10 System Architecture Register Address Summary Sheet 11 System Architecture Register Address Summary Sheet 12 Clock Manager Introduction Clocks and Power Manager Clock Manager Power Manager Introduction PWM SSP Retains Power in SleepOST Ficp I2C MMC 1 32.768 kHz Oscillator Core Phase Locked Loop2 3.6864 MHz Oscillator 5 147.46 MHz Peripheral Phase Locked Loop 4 95.85 MHz Peripheral Phase Locked LoopCore PLL Output Frequencies for 3.6864 MHz Crystal Sdram Hardware Reset Resets and Power ModesClock Gating Watchdog Reset Completing a Watchdog Reset Gpio ResetInvoking Gpio Reset Behavior During Gpio Reset Turbo Mode Run ModeCompleting Gpio Reset Entering Turbo Mode Behavior in Turbo Mode Idle ModeExiting Turbo Mode Entering Idle Mode Exiting Idle Mode Behavior in Idle ModeFrequency Change Sequence Preparing for a Frequency Change Sequence Behavior During the Frequency Change Sequence Invoking the Frequency Change Sequence Completing the Frequency Change Sequence 8 33-MHz Idle Mode Behavior in 33-MHz Idle Mode Entering 33-MHz Idle Mode Exiting 33-MHz Idle Mode Sleep ModeSleep Mode External Voltage Regulator Requirements Entering Sleep Mode Preparing for Sleep Mode Clocks and Power Manager Exiting Sleep Mode Behavior in Sleep Mode Clocks and Power Manager Power Mode Entry Sequence Table Power Mode SummaryPower Mode Exit Sequence Table Sheet 1 Idle Power Mode Exit Sequence Table Sheet 2 Power Mode Supply Source Module Turbo Run Power Manager Registers Pmcr Bit Definitions Power Manager Control Register PmcrPmcr Idae Pcfr Bit Definitions Power Manager General Configuration Register PcfrPcfr Opde Pwer Bit Definitions Power Manager Wake-Up Enable Register PwerWertc Pwer 10. Prer Bit Definitions Power Manager Rising-Edge Detect Enable Register Prer0x40F00010 Prer 11. Pfer Bit Definitions Power Manager Falling-Edge Detect Enable Register Pfer0x40F00014 Pfer 12. Pedr Bit Definitions Power Manager Gpio Edge Detect Status Register Pedr0x40F00018 Pedr 13. Pssr Bit Definitions Sheet 1 Power Manager Sleep Status Register PssrPssr RDH 13. Pssr Bit Definitions Sheet 2 Power Manager Scratch Pad Register Pspr14. Pspr Bit Definitions CPU VFS 15. Pmfw Register Bitmap and Bit Definitions Power Manager Fast Sleep Walk-up Configuration Register Pmfw 17. PGSR1 Bit Definitions 16. PGSR0 Bit DefinitionsPGSR0 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 Bit Reset 0x40F00028 Reset Controller Status Register Rcsr18. PGSR2 Bit Definitions PGSR2 Clocks Manager Registers Core Clock Configuration Register Cccr19. Rcsr Bit Definitions Rcsr 0x41300000 20. Cccr Bit DefinitionsBit Reserved Multiplier = 21. Cken Bit Definitions Sheet 1 Clock Enable Register Cken 21. Cken Bit Definitions Sheet 2 Description I2S Unit Clock EnableCKEN8 CKEN5 Oscillator Configuration Register Oscc Coprocessor 14 Clock and Power Management22. Oscc Bit Definitions 23. Coprocessor 14 Clock and Power Management Summary Core Clock Configuration Register Cclkcfg24. Cclkcfg Bit Definitions Power-On-Reset Considerations Power Mode Register PwrmodePower Supply Connectivity External Hardware Considerations Driving the Crystal Pins from an External Clock Source Clocks and Power Manager Register SummaryPower Manager Register Summary Clocks Manager Register Locations 27. Power Manager Register Summary Gpio Operation General-Purpose I/O Gpio Alternate Functions General-Purpose I/O Block Diagram Gpio Alternate Functions Sheet 1 Gpio Alternate Functions Sheet 2 MMCCS0 ALTFN1OUT Gpio Alternate Functions Sheet 3Mbgnt ALTFN1OUT Gpio Alternate Functions Sheet 4 Gpio Register DefinitionsGpio Register Definitions Sheet 1 Gpio Register Definitions Sheet 2 Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2GPLR0 Bit Definitions GPLR0 GPLR1 Bit Definitions Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2GPLR2 Bit Definitions GPLR1 GPDR1 Bit Definitions GPDR0 Bit DefinitionsGPDR2 Bit Definitions 10. GPSR1 Bit Definitions GPSR0 Bit DefinitionsGPSR0 PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 12. GPCR0 Bit Definitions 11. GPSR2 Bit Definitions13. GPCR1 Bit Definitions GPCR2 GPCR2 Bit Definitions 16. GRER1 Bit Definitions 15. GRER0 Bit Definitions17. GRER2 Bit Definitions 19. GFER1 Bit Definitions 18. GFER0 Bit DefinitionsGFER2 Bit Definitions 21. GEDR0 Bit Definitions Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR222. GEDR1 Bit Definitions GEDR2 GEDR2 Bit Definitions 25. GAFR0U Bit Definitions 24. GAFR0L Bit DefinitionsGAFR0L AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0 27. GAFR1U Bit Definitions 26. GAFR1L Bit DefinitionsGAFR1L GAFR1U 29. GAFR2U Bit Definitions 28. GAFR2L Bit DefinitionsGAFR2L GAFR2U Interrupt Controller Operation Interrupt Controller Interrupt Controller Register Definitions Interrupt Controller Block Diagram Interrupt Controller Level Register Iclr Interrupt Controller Mask Register Icmr30. Icmr Bit Definitions Icmr 31. Iclr Bit Definitions Interrupt Controller Control Register Iccr32. Iccr Bit Definitions 34. Icfp Bit Definitions 33. Icip Bit Definitions 35. Icpr Bit Definitions Sheet 1 Interrupt Controller Pending Register IcprIcpr IS9 IS8 35. Icpr Bit Definitions Sheet 2 Network SSP Service Request Interrupt PendingIS14 IS13 IS12 IS11 IS10 IS16 36. List of First-Level Interrupts Sheet 1 35. Icpr Bit Definitions Sheet 3System Integration Unit Bit Position Source Unit Real-Time Clock Operation Real-Time Clock RTC36. List of First-Level Interrupts Sheet 2 RTC Trim Register Rttr RTC Register Definitions Rttr Bit Definitions RTC Alarm Register Rtar38. Rtar Bit Definitions RTC Status Register Rtsr RTC Counter Register Rcnr39. Rcnr Bit Definitions Rcnr Oscillator Frequency Calibration Trim Procedure40. Rtsr Bit Definitions Trim Example #1 Measured Value Has No Fractional Component Rttr Value CalculationsTrim Example #2 Measured Value Has a Fractional Component Maximum Error Calculation Versus RTC Accuracy Operating System OS Timer OS Timer Register Definitions Watchdog Timer OperationOS Timer Match Register 0-3 OSMRx 41. OSMRx Bit Definitions OS Timer Interrupt Enable Register Oier42. Oier Bit Definitions OSMR3, OSMR2, OSMR1 OS Timer Count Register Oscr OS Timer Watchdog Match Enable Register OwerOS Timer Status Register Ossr 43. Ower Bit Definitions Pulse Width Modulator 0x40A00014 Bit Reset ? ? ? ? ? ? ? ? BitsPulse Width Modulator Operation Ossr Bit Definitions 1.1 Interdependencies PWMn Block Diagram Power Management Requirements Reset SequenceRegister Descriptions PWM Control Registers PWMCTRLn 46. PWMCTRLn Bit Definitions PWM Duty Cycle Registers PWMDUTYn0x40B00000 Prescale 47. PWMDUTYn Bit Definitions PWM Period Control Register PWMPERVALnPWMDUTY0, PWMDUTY1 Fdcycle Dcycle 48. PWMPERVALn Bit Definitions Pulse Width Modulator Output Wave Example0x40B00008 Gpio Register Locations System Integration Unit Register Summary49. Gpio Register Addresses Sheet 1 Interrupt Controller Register Locations OS Timer Register LocationsReal-Time Clock Register Locations Pulse Width Modulator Register Locations 52. OS Timer Register Addresses Sheet 253. Pulse Width Modulator Register Addresses DMA Description Dmac Block Diagram DREQ10 and PREQ370 Signals Signal DescriptionsDmac Signal List Signal Signal Type To/From Definition In/Out DMA Channel Priority Scheme Dmairq Signal Channel Priority Channel Priority if all channels are running concurrently DMA Descriptors No-Descriptor Fetch ModePriority Schemes Examples DMA Channel Priority No-Descriptor Fetch Mode Channel State Descriptor Fetch Mode DMA Controller Servicing an Interrupt Channel States Byte Transfer Order Read and Write Order Little Endian Transfers Trailing Bytes Servicing Internal Peripherals Transferring Data Dcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg = DMA Quick Reference for Internal Peripherals Sheet 1 Quick Reference for DMA ProgrammingDcmd Drcmr DMA Quick Reference for Internal Peripherals Sheet 2 Servicing Companion Chips and External PeripheralsUnit Function Fifo Address Width Burst Size Source DMA Controller Memory-to-Memory Moves DMA Interrupt Register Dint Dmac RegistersDMA Channel Control/Status Register DCSRx Dint Bit Definitions RUN DCSRx Bit Definitions Sheet 1Reqpend Stopstate Endintr Startintr Buserrintr DCSRx Bit Definitions Sheet 2 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA Descriptor Address Registers DDADRx DMA Request to Channel Map Registers DRCMRxDRCMRx Bit Definitions Chlnum DDADRx Bit Definitions DMA Source Address RegistersDescriptor Address Stop 10. DSADRx Bit Definitions DMA Target Address Registers DTADRxSource Address Srcaddr 11. DTADRx Bit Definitions DMA Command Registers DCMDxTarget Address Trgaddr Incsrcaddr 12. DCMDx Bit Definitions Sheet 1Endian Width Size Endian 12. DCMDx Bit Definitions Sheet 2Width Length Examples Example 1. How to set up and start a channel Struct longddadr longdsadr longdtadr shortlength shortdcmd 13. DMA Controller Register Summary Sheet 1 DMA Controller Register Summary 13. DMA Controller Register Summary Sheet 2 13. DMA Controller Register Summary Sheet 3 13. DMA Controller Register Summary Sheet 4 13. DMA Controller Register Summary Sheet 5 Memory Controller Sdram Interface Overview Functional Description Static Memory Interface / Variable Latency I/O Interface 3 16-Bit PC Card / Compact Flash Interface Memory System Examples Sdram Memory System Example Static Memory System Example Device Transactions Memory AccessesBus Operation Burst Size Words Bits Reads and Writes Synchronous Dram Memory InterfaceAborts and Nonexistent Memory Sdram Mdcnfg Register Mdcnfg Mdcnfg Bit Definitions Sheet 1 Mdcnfg Bit Definitions Sheet 2 DNB2 Mdcnfg Bit Definitions Sheet 3DADDR2 DLATCH2 Mdmrs Bit Definitions Sheet 1 Sdram Mode Register Set Configuration Register Mdmrs Mdmrs Bit Definitions Sheet 2 Low-Power Sdram Mode Register Set Configuration Register Mdmrslp Register Bit Definitions Sdram Mdrefr Register Mdrefr0X4800 Mdmrslp Mdrefr Mdrefr Bit Definitions Sheet 1APD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PIN DRI 0 1 0 0 1 * * 1 Mdrefr Bit Definitions Sheet 21 1 1 1 1 1 1 Mdrefr Bit Definitions Sheet 3 Fixed-Delay or Return-Clock Data LatchingAPD Sdram Addressing Modes Sdram Memory OptionsSample Sdram Memory Size Options Number Chips Partition Size ‘0’ # Bits1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32 Col Data MA2410 2x13x10x16 ‘0’ Not Valid illegal addressing combination # Bits External Address pins at Sdram RAS Time MA20 MA24 MA23BA0 A10 BA1 BA0 MA24 A11 A10 Memory Controller A12 Sdram Command Overview 12. Sdram Mode Register Opcode Table 11. Sdram Command EncodingSdram Waveforms Data Sdclk SDRAMreadsamebankdiffrow SDCLK1 SDCKE1 SDRAMwrite Synchronous Static Memory Interface Synchronous Static Memory Configuration Register Sxcnfg 0x4800001C 13. Sxcnfg Bit Definitions Sheet 1Sxcnfg SXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2 SXLATCH2 Sxcnfg Bit Definitions Sheet 2SXRL2 SXCL2 SXEN2 SXLATCH0 13. Sxcnfg Bit Definitions Sheet 3 Sxcnfg Bit Definitions Sheet 4 Smrom Memory OptionsSXCL0 SXEN0 Smrom 16. Sxmrs Bit Definitions Synchronous Static Memory Timing DiagramsSxmrs SXMRS2 Sdclk Sdcke Non-SDRAM Timing Sxmem Operation Memclk SDCLK0 Mdrefr 17. Read Configuration Register Programming Values 12shows the burst-of-eight read timing diagram Non-SDRAM Timing Flash Read Timing Diagram Asynchronous Static Memory 4.2 K3 Synchronous StrataFlash ResetStatic Memory Interface Sram 20 -Bit Bus Write Access 19 -Bit Bus Write AccessData Size MA10 DQM30 Data Size MA0 DQM10 22 -Bit Byte Address Bit MA0 for Reads Based on DQM10 21 -Bit Byte Address Bits MA10 for Reads Based on DQM3023. SA-1111 Register Bit Definitions Asynchronous Static Memory Control Registers MSCx MSC0 24. MSC0/1/2 Bit Definitions Sheet 1MSC1 MSC2 Bits Access Name RRR1/3/5 RDN1/3/5 Reset RDF1/3/524. MSC0/1/2 Bit Definitions Sheet 2 Sram 24. MSC0/1/2 Bit Definitions Sheet 3 Timing Memory Clocks MSCxRTx Device ROM InterfaceNOE NWE NOE Clkmem ROM Timing Diagrams and Parameters RDN+1 Sram Interface Overview Sram Timing Diagrams and Parameters 20shows the timing for Sram writes Variable Latency I/O Vlio Interface Overview RDF+1+Waits RRR*2+1 Variable Latency I/O Timing Diagrams and Parameters RDF+1+Waits Flash Memory Interface Flash Memory Timing Diagrams and Parameters CMD Data 23. Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes 16-Bit PC Card/Compact Flash Interface Expansion Memory Timing Configuration Register26. MCMEM0/1 Bit Definitions MCMEM0 28. MCIO0/1 Bit Definitions 27. MCATT0/1 Bit DefinitionsMCATT0 MCATT1 MCMEMxASST XASSTHOLD XASSTWAIT + 29. Card Interface Command Assertion Code Table 30. Mecr Bit Definition Expansion Memory Configuration Register MecrMecr CIT NOS 26 -Bit PC Card Memory Map 3 16-Bit PC Card Overview 32. Common Memory Space Read Commands 31. Common Memory Space Write Commands33. Attribute Memory Space Write Commands 34. Attribute Memory Space Read Commands 38 -Bit I/O Space Read Commands nIOIS16 = 37 -Bit I/O Space Write Commands nIOIS16 =External Logic for 16-Bit PC Card Implementation DIR Socket 29 -Bit PC Card Memory or I/O 16-Bit Half-word Access Expansion Card Interface Timing Diagrams and Parameters Companion Chip Interface 30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device 32. Variable Latency IO 31. Alternate Bus Master Mode Alternate Bus Master Mode NVDDFAULT/nBATTFAULT with Pmcridae Disabled Gpio ResetNVDDFAULT/nBATTFAULT with Pmcridae Enabled Alternate Booting Options and Settings for Boot MemoryBoot Time Defaults Bootdef Read-Only Register Bootdef 41. Valid Boot Configurations Based on Processor Type 40. Bootdef BitmapBootdef PKG Type Boot SEL Sxcnfg Boot-Time Configurations 34. Smrom Boot Time Configurations and Register Defaults Smrom Memory Interface Reset and InitializationMdrefr 03CA 7FFF 42. Memory Controller Pin Reset Values Hardware, Watchdog, or Sleep Reset OperationPin Name PXA255 Processor Reset Value Memory Controller Physical Address Symbol Register Name Gpio Reset ProcedureMemory Controller Register Summary 43. Memory Controller Register Summary Sheet 1 43. Memory Controller Register Summary Sheet 2 LCD Controller LCD Controller Features LCD Controller Block Diagram Pin Descriptions LCD Controller OperationEnabling the Controller Pin Descriptions Detailed Module Descriptions Resetting the ControllerDisabling the Controller Input FIFOs Temporal Modulated Energy Distribution Tmed Dithering Lookup Palette Compare Range for Tmed LCD Controller Pin Usage Output FIFOs 6 DMA Pixel Data Pins LDDxPassive Display Timing Active Display Timing External Palette Buffer LCD External Palette and Frame Buffers Palette Buffer Format External Frame Buffer Bits Per Pixel Data Memory Organization 10 Bits Per Pixel Data Memory Organization Passive Mode FrameBufferSize = Functional Timing 12. Passive Mode Start-of-Frame Timing Hsync Lbias Vsync Lfclk Vsync Llclk Hsync Lbias Register Descriptions LCD Controller Control Register 0 LCCR0 LCD Controller LDD LCD Controller Data Pin Utilization Sheet 1 LCD Controller Data Pin Utilization Sheet 2 Single Passive Screen Portion Pins LCCR0 Bit Definitions Sheet 1 Reset X X X X X X X X X X XLCCR0 0x44000000 Bit Reserved LCCR0 Bit Definitions Sheet 2 LCD Controller Control Register 1 LCCR1QDM DIS DPD PAS EFM IUM SFM LDM SDS CMS ENB LCD Controller LCCR1 Bit Definitions LCD Controller Control Register 2 LCCR2BLW ELW HSW PPL BLW LCD Controller LCCR2 Bit Definitions LCD Controller Control Register 3 LCCR3BFW EFW VSW LPP BFW LCD Controller LCD Controller LCCR3 Bit Definitions Sheet 1 Reset X X X X 0 0 00x4400000C Bit Reserved DPC BPP LCD Controller DMA Reset X X XFrame Descriptors LCCR3 Bit Definitions Sheet 2 LCD DMA Frame Source Address Registers FSADRx LCD DMA Frame Descriptor Address Registers FDADRxFDADRx Bit Definitions FDADR0 FSADRx Bit Definitions LCD DMA Frame ID Registers FIDRxFIDRx Bit Definitions LCD DMA Command Registers LDCMDx LDCMD0 10. LDCMDx Bit DefinitionsLDCMD1 PAL 11. FBRx Bit Definitions LCD DMA Frame Branch Registers FBRxBint BRA 0 0 0 0 X X 0 Bits Name Description LCD Controller Status Register Lcsr LCD Controller Lcsr Bit Definitions Sheet 1 0x44000038 Bit Reset X XX X EOF IUU IUL ABC BER SOF LDD 12. Lcsr Bit Definitions Sheet 2 LCD Controller Interrupt ID Register Liidr13. Liicr Bit Definitions Sint BS EOF QD OU IUU IUL ABC BER SOF LDD 14. Trgbr Bit Definitions Tmed RGB Seed Register TrgbrTBS TRS Tmed Control Register TCR 15. TCR Bit Definitions LCD Controller Register Summary16. LCD Controller Register Summary Sheet 1 16. LCD Controller Register Summary Sheet 2 LCD Controller External Interface to Synchronous Serial Peripherals Signal DescriptionExternal Interface to Codec Name Direction Description Data Transfer Data FormatsSerial Data Formats for Transfer to/from Peripherals SSP Format Details Sspsclk Sspsfrm SPI Format DetailsSspsclk Sspsfrm MSB LSB Sspsclk Sspsfrm Ssptxd Ssprxd Microwire Format Details Parallel Data Formats for Fifo Storage National Microwire* Frame Format Using DMA Data Transfers Using Programmed I/O Data TransfersFifo Operation and Data Transfers Baud-Rate Generation SSP Control Register 0 SSCR0 SSP Serial Port Registers SSCR0 Bit Definitions Data Size Select DSSSSP Control Register 0 SSCR0 SCR Frame Format FRF Synchronous Serial Port Enable SSEExternal Clock Select ECS Serial Clock Rate SCR SSP Control Register 1 SSCR1SSCR1 Bit Definitions Sheet 1 Transmit Fifo Interrupt Enable TIE Receive Fifo Interrupt Enable RIELoop Back Mode LBM SSCR1 Bit Definitions Sheet 2 Serial Clock Polarity SPO Serial Clock Phase SPHSspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Transmit Fifo Interrupt/DMA Threshold TFT Microwire Transmit Data Size MwdsReceive Fifo Interrupt/DMA Threshold RFT Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd TFT and RFT Values for DMA Servicing SSP Data Register SsdrSsdr Bit Definitions SSP Status Register Sssr Sssr Bit Definitions Transmit Fifo Not Full Flag TNFRFL TFL ROR RFS TFS BSY RNE TNF RFL Receive Fifo Service Request Flag RFS Transmit Fifo Service Request Flag TFSReceive Fifo Not Empty Flag RNE SSP Busy Flag BSY Receive Fifo Level RFL SSP Controller Register SummarySSP Controller Register Summary Address Abbreviation Full Name Synchronous Serial Port Controller Signal Name Input/Output Description I2C Signal DescriptionSDA SCL 2C Device Definition I2C Bus Definitions Operational Blocks Mode Description2 I2C Bus Interface Modes Modes of Operation Start and Stop Bit Definitions Start and Stop Bus StatesStop Star Condition No Start or Stop Condition Start ConditionStop Condition Start ACK NAKACK ACK Stop NAK Serial Clock Line SCL Generation I2C Bus OperationData and Addressing Management Addressing a Slave Device 3 I2C Acknowledge Arbitration Polling SDA Arbitration SCL Arbitration Arbitration Procedure of Two Masters Master Operations 2C Master Mode Definition Action OperationMaster Transactions Sheet 1 Master Transactions Sheet 2 Master-Receiver Read from Slave-Transmitter Slave Operations Slave Transactions 2C Slave Action Mode Definition Operation ACK Stop General Call AddressNAK Stop Least Second General Call Address Second Byte Definitions Initialize Unit Slave Mode Programming ExamplesWrite n Bytes as a Slave Read n Bytes as a Slave Write 1 Byte as a Master Master Programming Examples Write 2 Bytes and Repeated Start Read 1 Byte as a Master Read 1 Byte as a Master Read 2 Bytes as a Master Send Stop Using the Abort Reset ConditionsGlitch Suppression Logic 1 I2C Bus Monitor Register Ibmr Register Definitions2 I2C Data Buffer Register Idbr Ibmr Bit Definitions Idbr Bit Definitions 3 I2C Control Register ICR10. ICR Bit Definitions Sheet 1 Disable interrupt 40301690 Bit Reset10. ICR Bit Definitions Sheet 2 Beie Irfie Iteie GCD IUE 4 I2C Status Register ISR Receive mode10. ICR Bit Definitions Sheet 3 2C Status Register 11. ISR Bit Definitions Sheet 140301698 Bit BED SAD 11. ISR Bit Definitions Sheet 2 5 I2C Slave Address Register Isar12. Isar Bit Definitions BED SAD Gcad IRF ITE ALD SSD IBB I2C Bus Interface Unit UARTs Feature List Full Function Uart Bluetooth UartStandard Uart Compatibility with Uart Signal Descriptions Sheet 1 Signal DescriptionsName Type Description RXD Uart Operational Description Uart Signal Descriptions Sheet 2LSB MSB Internal Register Descriptions Reset Receive Buffer Register RBR Register AccessedUart Register Addresses as Offsets of a Base RBR Bit Definitions Divisor Latch Registers DLL and DLH Transmit Holding Register THRTHR Bit Definitions DLL Bit Definitions Interrupt Enable Register IERDLH Bit Definitions IER Bit Definitions Interrupt Identification Register IIR IIR Bit Definitions Sheet 1 Interrupt ConditionsPriority Level Interrupt origin FIFOES10 Fcrresetrf Interrupt ID Bits Interrupt SET/RESET FunctionIIR Bit Definitions Sheet 2 10. Interrupt Identification Register Decode Sheet 1 10. Interrupt Identification Register Decode Sheet 2 Fifo Control Register FCR11. FCR Bit Definitions Sheet 1 ITL 11. FCR Bit Definitions Sheet 2 Line Control Register LCR Base+0x0C 12. LCR Bit DefinitionsUart Dlab Stkyp EPS PEN STB WLS1 WLS0 13. LSR Bit Definitions Sheet 1 Line Status Register LSRFifoe Temt Tdrq 13. LSR Bit Definitions Sheet 2 13. LSR Bit Definitions Sheet 3 14. MCR Bit Definitions Sheet 1 Modem Control Register MCRUart Loop OUT2 OUT1 RTS DTR 14. MCR Bit Definitions Sheet 2 Modem Status Register MSRBase+0x10 Modem Control Register 15. MSR Bit Definitions Character Timeout Indication Interrupt Fifo Interrupt Mode OperationScratchpad Register SPR Receive Interrupt DMA Requests Fifo Polled Mode OperationTransmit Interrupt Trailing Bytes in the Receive Fifo Slow Infrared Asynchronous InterfaceInfrared Selection Register ISR 17. ISR Bit Definitions Operation IR Transmit and Receive Example 18. Ffuart Register Summary Uart Register Summary19. Btuart Register Summary Sheet 1 Dlab Bit Name Description 20. Stuart Register Summary 19. Btuart Register Summary Sheet 2 21. Flow Control Registers in Btuart and Stuart Uart Register DifferencesBtmcr Btmsr Ficp Operation Ficp Signal Description PPM Modulation Encodings 11.2.1 4PPM Modulation Address Field Frame FormatControl Field Data Field Baud Rate Generation CRC FieldReceive Operation Transmit Operation Transmit and Receive FIFOs Ficp Register Definitions Trailing or Error Bytes in the Receive Fifo ICCR0 Bit Definitions Sheet 1 Ficp Control Register 0 ICCR0 TXE ICCR0 Bit Definitions Sheet 2TUS LBM ICCR1 Bit Definitions Ficp Control Register 1 ICCR1 ICCR2 Bit Definitions Ficp Control Register 2 ICCR2 Icrd Bit Definitions Ficp Data Register Icdr ICSR0 Bit Definitions Sheet 1 Ficp Status Register 0 ICSR0FRE RFS TUR ICSR0 Bit Definitions Sheet 2EIF ICSR1 Bit Definitions Ficp Status Register 1 ICSR1 Ficp Register Summary Ficp Register Summary USB Overview USB Device Controller Endpoint Configuration Device ConfigurationUSB Protocol IN/OUT Bit Encoding Signalling LevelsUSB States Bus State UDC+/UDC- Pin Levels Nrzi Bit Encoding Example Field Formats Packet Formats IN, OUT, and Setup Token Packet FormatToken Packet Type Start of Frame Packet Type Data Packet Type Transaction FormatsHandshake Packet Type Bulk Transaction Type Control Transaction Type Isochronous Transaction TypeBulk Transaction Formats Isochronous Transaction Formats Interrupt Transaction Type UDC Device Requests10. Interrupt Transaction Formats 11. Host Device Request Summary ConfigurationRequest Name UDC Hardware Connection Self-Powered Device When GPIOn and GPIOx are the Same Pin When GPIOn and GPIOx are Different Pins UDC Operation Bus-Powered DevicesCase 1 EP0 Control Read Case 2 EP0 Control Read with a Premature Status Stage 12-14 Intel PXA255 Processor Developer’s Manual Software Enables the DMA Case 4 EP0 No Data CommandCase 5 EP1 Data Transmit BULK-IN Case 6 EP2 Data Receive BULK-OUT Software Enables the EP1 Interrupt Case 7 EP3 Data Transmit ISOCHRONOUS-IN Software Enables DMASoftware Allows the Megacell to Handle the Transaction Software Enables the SOF Interrupt Software Enables the EP3 InterruptCase 8 EP4 Data Receive ISOCHRONOUS-OUT Intel PXA255 Processor Developer’s Manual 12-19 Case 9 EP5 Data Transmit INTERRUPT-IN Case 10 Reset Interrupt Case 11 Suspend Interrupt UDC Register DefinitionsCase 12 Resume Interrupt UDC Control Register Udccr UDC Enable UDE12. Udccr Bit Definitions Reset Interrupt Mask REM Reset Interrupt Request RstirUDC Active UDA UDC Resume RSM ACK Response Enable ACK Control ModeUDC Control Function Register Udccfr 13. UDC Control Function Register OUT Packet Ready OPR UDC Endpoint 0 Control/Status Register UDCCS0Packet Ready IPR 14. UDCCS0 Bit Definitions Flush Tx Fifo FTF Device Remote Wakeup Feature DrwfSent Stall SST Force Stall FST Transmit Fifo Service TFS Setup Active SAUDC Endpoint x Control/Status Register UDCCS1/6/11 15. UDCCS1/6/11 Bit Definitions Transmit Underrun TUR Transmit Packet Complete TPCBit 6 Reserved Transmit Short Packet TSP UDC Endpoint x Control/Status Register UDCCS2/7/1216. UDCCS2/7/12 Bit Definitions DMA Enable DME Receive Fifo Service RFSReceive Packet Complete RPC Bit 2 Reserved Receive Short Packet RSP UDC Endpoint x Control/Status Register UDCCS3/8/1317. UDCCS3/8/13 Bit Definitions Bits 64 Reserved UDC Endpoint x Control/Status Register UDCCS4/9/14 18. UDCCS4/9/14 Bit Definitions Receive Overflow ROF Bits 54 Reserved UDC Endpoint x Control/Status Register UDCCS5/10/1519. UDCCS5/10/15 Bit Definitions Sheet 1 19. UDCCS5/10/15 Bit Definitions Sheet 2 UDC Interrupt Control Register 0 UICR0 20. UICR0 Bit Definitions Interrupt Mask Endpoint x IMx, Where x is 0 throughUICR0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 UDC Interrupt Control Register 1 UICR1 Interrupt Mask Endpoint x IMx, where x is 8 through21. UICR1 Bit Definitions UICR1 Endpoint 0 Interrupt Request IR0 UDC Status/Interrupt Register 0 USIR0Endpoint 1 Interrupt Request IR1 22. USIR0 Bit Definitions Endpoint 3 Interrupt Request IR3 Endpoint 2 Interrupt Request IR2Endpoint 4 Interrupt Request IR4 Endpoint 5 Interrupt Request IR5 Endpoint 8 Interrupt Request IR8 UDC Status/Interrupt Register 1 USIR1Endpoint 9 Interrupt Request IR9 Endpoint 10 Interrupt Request IR10 UDC Frame Number High Register Ufnhr Isochronous Packet Error Endpoint 9 IPE9 Isochronous Packet Error Endpoint 4 IPE4UDC Frame Number MSB Fnmsb 24. Ufnhr Bit Definitions UDC Frame Number Low Register Ufnlr Isochronous Packet Error Endpoint 14 IPE14UDC Byte Count Register x UBCR2/4/7/9/12/14 Start of Frame Interrupt Mask SIM Endpoint x Byte Count BC UDC Endpoint 0 Data Register UDDR026. UBCR2/4/7/9/12/14 Bit Definitions UDC Endpoint x Data Register UDDR2/7/12 UDC Endpoint x Data Register UDDR1/6/1127. UDDR0 Bit Definitions 28. UDDR1/6/11 Bit Definitions UDC Endpoint x Data Register UDDR4/9/14 UDC Endpoint x Data Register UDDR3/8/1329. UDDR2/7/12 Bit Definitions 30. UDDR3/8/13 Bit Definitions UDC Endpoint x Data Register UDDR5/10/15 USB Device Controller Register Summary31. UDDR4/9/14 Bit Definitions 32. UDDR5/10/15 Bit Definitions Ufnhr 33. USB Device Controller Register Summary Sheet 2Ufnlr 33. USB Device Controller Register Summary Sheet 3 AC’97 Controller Unit Example AC-link Signal Configuration StepsExternal Interface to CODECs Name Direction Description summary Supported Data Stream Formats Sheet 1 AC-link Digital Serial Interface ProtocolSDATAIN0 SDATAIN1 Channel Slots Comments Supported Data Stream Formats Sheet 2 AC-link Audio Output Frame SdataoutSync AC-link Audio Output Frame Slot 1 Command Address Port Slot 0 Tag Phase Slot 3 PCM Playback Left Channel Slot 2 Command Data PortSlot 1 Bit Definitions Slot 2 Bit Definitions Slot 4 PCM Playback Right Channel AC-link Audio Input Frame SdatainSlot 5 Modem Line Codec Slots 6-11 Reserved Sync Input Slot 1 Bit Definitions Sheet 1 Slot 1 Status Address Port/SLOTREQ bitsBit Description Slot 3 PCM Record Left Channel Slot 2 Status Data PortSlot 4 PCM Record Right Channel Slot 5 Optional Modem Line Codec Powering Down the AC-link AC-link Low Power ModeSlots 7-11 Reserved Slot 12 I/O Status Wake up triggered by the Codec Waking up the AC-link Warm AC’97 Reset Cold AC’97 ResetAcunit Operation Wake Up Triggered by the Acunit Initialization 13-16 Intel PXA255 Processor Developer’s Manual Clocks and Sampling Frequencies Operational Flow for Accessing Codec Registers Receive Fifo Errors Transmit Fifo ErrorsFIFOs Registers Interrupts GCR Bit Definitions Sheet 1 Global Control Register GCR GCR Bit Definitions Sheet 2 Global Status Register GSRWarmrst Coldrst Cdone Sdone GSR Bit Definitions Sheet 1Rdcs Secres Prires SCR PCR Mint Point Piint GSR Bit Definitions Sheet 2 PCM-Out Control Register PocrPocr Bit Definitions Sheet 1 Pocr Bit Definitions Sheet 2 PCM-In Control Register Picr10. Picr Bit Definitions PCMIn Status Register Pisr PCM-Out Status Register Posr11. Posr Bit Definitions 12. Pisr Bit Definitions PCM Data Register Pcdr Codec Access Register CAR13. CAR Bit Definitions 14. Pcdr Bit Definitions Mic-In Status Register Mcsr Mic-In Control Register Mccr15. Mccr Bit Definitions Mccr Register 16. Mcsr Bit Definitions Mic-In Data Register Mcdr17. Mcdr Bit Definitions Micindat Modem-In Control Register Micr Modem-Out Control Register Mocr18. Mocr Bit Definitions Mocr Register Modem-In Status Register Misr Modem-Out Status Register Mosr19. Micr Bit Definitions 20. Mosr Bit Definitions 21. Misr Bit Definitions Modem Data Register Modr22. Modr Bit Definitions Modemdat 11. Modem Transmit and Receive Operation Accessing Codec Registers Processor Bit Physical 23. Address Mapping for Codec Registers Sheet 1Address for a Primary Secondary Audio Codec Modem Codec 23. Address Mapping for Codec Registers Sheet 2 24. Register Mapping Summary 13.9 AC’97 Register Summary 13-36 Intel PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound I2S Controller GP29/SDATAIN GP32/SYSCLK Controller Operation Disabling and Enabling Audio Record Disabling and Enabling Audio Replay Receive Fifo Errors Transmit Fifo ErrorsSerial Audio Clocks and Sampling Frequencies 14.5.2 I2S and MSB-Justified Serial Audio Formats Fifo and Memory FormatSupported Sampling Frequencies Sysclk = Bitclk = I2S Data Formats 16 bits Serial Audio Controller Global Control Register SACR0 Registers SACR0 Bit Definitions Special purpose Fifo Read/Write function Fifo Write/Read table Suggested Tfth and Rfth for DMA servicingTfth and Rfth Values for DMA Servicing Efwr Strf Enlbf SACR1 Bit DefinitionsDrpl Drec SASR0 Bit Definitions Serial Audio Clock Divider Register SadivRFL TFL Sadiv Bit Definitions Serial Audio Interrupt Clear Register SaicrSaicr Bit Definitions Serial Audio Data Register Sadr Serial Audio Interrupt Mask Register Saimr10. Saimr Bit Descriptions 11. Sadr Bit Descriptions 14.8 I2S Controller Register Summary Transmit and Receive Fifo Accesses Through the Sadr Address Register Description Paddr90 Name 12. Register Memory Map MultiMediaCard Controller MMC Data Token Format Command Token FormatSPI Data Token Format Mmdat Mmcmd CRC MMC Controller Functional Description Intel PXA255 Processor Developer’s Manual 15-5 MMC Controller Reset Signal DescriptionMMC Signal Description Card Initialization Sequence MMC Mode SPI Mode Error Detection Clock Control Response Data Fifo Mmcres Data FIFOsReceive Data FIFO, Mmcrxfifo Transmit Data FIFO, Mmctxfifo DMA and Program I/O Card Communication Protocol Mmcclkrt Mmcspi Mmcresto Basic, No Data, Command and Response Sequence Block Data Write Stream Data Write Block Data Read Stream Data Read Busy Sequence MultiMediaCard Controller Operation Enabling SPI ModeSPI Functionality Start and Stop Clock Erase No Data Command and Response SequenceSingle Data Block Write Single Block Read Multiple Block Read Multiple Block Write Stream Read Stream Write Mmcstrpcl Register MMC Controller Registers Mmcstrpcl Bit Definitions MMCStatus Register MmcstatMmcstat Bit Definitions Sheet 1 Strpcl Mmcstat Bit Definitions Sheet 2 Mmcclkrt Register Mmcclkrt Mmcclk Bit Definitions Mmcspi Register MmcspiMmcspi Bit Definitions Sheet 1 Mmcspi Bit Definitions Sheet 2 Mmccmdat Register MmccmdatMmccmdat Bit Definitions Sheet 1 Mmccmdat Bit Definitions Sheet 2 Mmcresto Register Mmcresto10. Mmcresto Bit Definitions 11. Mmcrdto Register Mmcrdto Register MmcrdtoReadto Specifies the length of time before a data read time-out Mmcnob Register Mmcnob Mmcblklen Register Mmcblklen12. Mmcblklen Bit Definitions 13. Mmcnob Bit Definitions Mmcimask Register Mmcimask Mmcprtbuf Register Mmcprtbuf14. Mmcprtbuf Bit Definitions 15. Mmcimask Bit Definitions Sheet 1 15. Mmcimask Bit Definitions Sheet 2 Mmcireg Register MmciregMmcimask Register MultiMediaCard Controller 4 3 2 1 16. Mmcireg Bit Definitions CMD Comm Mode Abbreviation Index 18. Command Index Values Sheet 1Mmccmd Register Mmccmd 17. Mmccmd Register 18. Command Index Values Sheet 2 Mmcargh Register Mmcargh 18. Command Index Values Sheet 3Mmcargl Register Mmcargl 19. Mmcargh Bit Definitions 21. MMCRES, Fifo Entry Mmcres Fifo22. MMCRXFIFO, Fifo Entry Responsedata 23. MMCTXFIFO, Fifo Entry MultiMediaCard Controller Register Summary24. MMC Controller Registers Sheet 1 Writedata 24. MMC Controller Registers Sheet 2 Network SSP Serial Port Features SSP Serial Port I/O Signals Processor and DMA Fifo AccessOperation Data Formats Trailing Bytes in the Receive Fifo 16-4 Intel PXA255 Processor Developer’s Manual TI Synchronous Serial Protocol* Details SPI Protocol Details Motorola SPI* Frame Protocol multiple transfers Serial Clock Phase SPH 16-8 Intel PXA255 Processor Developer’s Manual Microwire* Protocol Details PSP Details Programmable Serial Protocol multiple transfers Sspspscmode Programmable Serial Protocol PSP ParametersSspspsfrmp Sspspstrtdly 11. TI SSP with SSCRTTE=1 and SSCRTTELP=0 Hi-Z on Ssptxd Motorola SPI Programmable Serial Protocol 16-16 Intel PXA255 Processor Developer’s Manual Baud-Rate Generation Fifo Operation 16-18 Intel PXA255 Processor Developer’s Manual SSCR0 SSCR0 Bit Definitions Sheet 1SCR SSE FRF DSS Edss SCR SSE SSCR0 Bit Definitions Sheet 2Data Size Select Edss DSS Sclkdir Sfrmdir Scfr Ttelp TTE EbceiSSCR1 SPH SPO LBM TIE RIE SSP Programmable Serial Protocol Register Sspsp Sspsp Bit Definitions Sheet 1 SSP Interrupt Test Register Ssitr SSP Time Out Register SstoSspsp Bit Definitions Sheet 2 Ssto Bit Definitions Test Transmit Fifo Service Request Ttfs Test Receive Fifo Service Request TrfsSsitr Bit Definitions Ssitr Sssr Sssr Bit Definitions Sheet 1BCE CSS TUR Tint Sssr Bit Definitions Sheet 2 Sssr Bit Definitions Sheet 3 Transmit Fifo Service RequestSSP Busy Receive Fifo not Empty 10. Nssp Register Address Map Network SSP Serial Port Register SummarySsdr Data TRANSMIT/RECEIVE Data 16-30 Intel PXA255 Processor Developer’s Manual Hardware Uart Hardware Uart Operation Uart Signal Descriptions 17-4 Intel PXA255 Processor Developer’s Manual Fifo Polled Mode Operation Fifo Interrupt Mode OperationCharacter Timeout Interrupt Receive Interrupt DMA Receive Programming Errors Fifo DMA Mode OperationDMA Error Handling Autoflow Control Removing Trailing Bytes In DMA ModeAuto-Baud-Rate Detection 17-8 Intel PXA255 Processor Developer’s Manual Intel PXA255 Processor Developer’s Manual 17-9 Transmit Holding Register THR Receive Buffer Register RBRDivisor Latch Registers DLL and DLH Bit Reserved Byte Bits Name Description 318 Divisor Latch Register High DLH Bit Definitions Interrupt Enable Register IERDLL DLH 0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name Physical Address Interrupt Enable Register IER? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description IIR Interrupt Identification Register IIRABL TOD IID NIP Interrupt Identification Register Decode Sheet 1 Priority Type Source Reset Control0x41600008 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 Interrupt Identification Register Decode Sheet 2 Fifo Control Register FCR10. FCR Bit Definitions Sheet 1 10. FCR Bit Definitions Sheet 2 Receive Fifo Occupancy Register for11. for Bit Definitions Auto-Baud Count Register ACR Auto-Baud Control Register ABR12. ABR Bit Definitions ABT 13. ACR Bit Definitions Line Control Register LCR14. LCR Bit Definitions Sheet 1 ACR 14. LCR Bit Definitions Sheet 2 Line Status Register LSRLine Control Register LCR PXA255 Processor Hardware Uart Dlab Stkyp EPS PEN STB WLS 0x41600014 Bit 15. LSR Bit Definitions Sheet 1? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits 15. LSR Bit Definitions Sheet 2 Modem Control Register MCRLine Status Register LSR PXA255 Processor Hardware Uart 0 0 0 0 Bits Name Description 16. MCR Bit Definitions Sheet 1 0x41600010 Bit Reset ? ? ? ? ? ? ? BitsPhysical Address Modem Control Register MCR AFE 16. MCR Bit Definitions Sheet 2 Modem Status Register MSR17. MSR Bit Definitions Sheet 1 Infrared Selection Register ISR Scratchpad Register SCR17. MSR Bit Definitions Sheet 2 18. SCR Bit Definitions 19. ISR Bit Definitions Hardware Uart Register Summary20. Hwuart Register Locations Sheet 1 Rxpl Txpl Xmode Rcveir Xmitir 20. Hwuart Register Locations Sheet 2 Intel PXA255 Processor Developer’s Manual 17-27