Contents

 

4-49

GPIO Register Addresses

4-44

4-50

Interrupt Controller Register Addresses

4-45

4-51

RTC Register Addresses

4-45

4-52

OS Timer Register Addresses

4-45

4-53

Pulse Width Modulator Register Addresses

4-46

5-1

DMAC Signal List

5-2

5-2

Channel Priority (if all channels are running concurrently)

5-4

5-3

Channel Priority

5-4

5-4

Priority Schemes Examples

5-5

5-5

DMA Quick Reference for Internal Peripherals

5-13

5-6

DINT Bit Definitions

5-17

5-7

DCSRx Bit Definitions

5-18

5-8

DRCMRx Bit Definitions

5-20

5-9

DDADRx Bit Definitions

5-21

5-10

DSADRx Bit Definitions

5-22

5-11

DTADRx Bit Definitions

5-23

5-12

DCMDx Bit Definitions

5-24

5-13

DMA Controller Register Summary

5-28

6-1

Device Transactions

6-7

6-2

MDCNFG Bit Definitions

6-9

6-3

MDMRS Bit Definitions

6-12

6-4

MDMRSLP Register Bit Definitions

6-14

6-5

MDREFR Bit Definitions

6-15

6-6

Sample SDRAM Memory Size Options

6-18

6-7

External to Internal Address Mapping for Normal Bank Addressing

6-19

6-8

External to Internal Address Mapping for SA-1111 Addressing

6-21

6-9

Pin Mapping to SDRAM Devices with Normal Bank Addressing

6-23

6-10

Pin Mapping to SDRAM Devices with SA1111 Addressing

6-25

6-11

SDRAM Command Encoding

6-28

6-12

SDRAM Mode Register Opcode Table

6-28

6-13

SXCNFG Bit Definitions

6-33

6-14

SXCNFG

6-36

6-15

Synchronous Static Memory External to Internal Address Mapping Options

6-37

6-16

SXMRS Bit Definitions

6-38

6-17

Read Configuration Register Programming Values

6-40

6-18

Frequency Code Configuration Values Based on Clock Speed

6-40

6-20

16-Bit Bus Write Access

6-44

6-19

32-Bit Bus Write Access

6-44

6-21

32-Bit Byte Address Bits MA[1:0] for Reads Based on DQM[3:0]

6-45

6-22

16-Bit Byte Address Bit MA[0] for Reads Based on DQM[1:0]

6-45

6-23

SA-1111 Register Bit Definitions

6-45

6-24

MSC0/1/2 Bit Definitions

6-47

6-25

Asynchronous Static Memory and Variable Latency I/O Capabilities

6-50

6-26

MCMEM0/1 Bit Definitions

6-60

6-27

MCATT0/1 Bit Definitions

6-61

6-28

MCIO0/1 Bit Definitions

6-61

6-29

Card Interface Command Assertion Code Table

6-62

6-30

MECR Bit Definition

6-63

6-31

Common Memory Space Write Commands

6-65

6-32

Common Memory Space Read Commands

6-65

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Intel® PXA255 Processor Developer’s Manual

Page 18
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Intel PXA255 manual Sxcnfg