Descriptor Fetch Mode | Intel PXA255 instruction

DMA Controller

7.The channel waits for the next request or continues with the data transfer until the DCMD[LENGTH] reaches zero.

8.The DDADR[STOP] is set to a 1 and the channel stops.

Figure 5-3summarizes typical No-Descriptor Fetch Mode operation.

Figure 5-3. No-Descriptor Fetch Mode Channel State

RESET (Hardware or Sleep)
DCSR[RUN]=0,			RUN=0
DCSR[NODESCFETCH]=1,
DSADR,DTADR,		Valid
DCMD programmed		Valid			Channel
DCMD programmed		descriptor
Uninitialized		descriptor
		not running			Error
		RUN=1
		No		DDADR[STOP] = 0
		descriptor		DDADR[STOP] = 0
DCMD[FLOWSRC] xor		descriptor
DCMD[FLOWSRC] xor		fetch	RUN=0
DCMD[FLOWTRG] = 1		(running)	RUN=0
		DCMD[FLOWSRC] &
		DCMD[FLOWTRG] = 0
	DCMD[FLOWSRC] xor
Wait	DCMD[FLOWTRG] = 1
for			Transferring
request	Request Asserted			Data
	Request Asserted
DDADR[STOP] = 1		DDADR[STOP] = 1			DCMD[LENGTH]≠ 0
DDADR[STOP] = 1		DDADR[STOP] = 1			& DCMD[FLOWSRC] = 0
					& DCMD[FLOWTRG] = 0
		Stopped

5.1.4.2Descriptor Fetch Mode

In Descriptor Fetch Mode, the DMAC registers are loaded from DMA descriptors in main memory. Multiple DMA descriptors can be chained together in a list. This allows a DMA channel to transfer data to and from a number of locations that are not contiguous. The descriptor’s protocol design allows descriptors to be added efficiently to the descriptor list of a running DMA stream.

A typical Descriptor Fetch Mode (DCSR[NODESCFETCH] = 0) operation follows:

1.The channel is in an uninitialized state after reset.

2.The software writes a descriptor address (aligned to a 16-byte boundary) to the DDADR register.

3.The software writes a 1 to the DCSR[RUN] bit.

4.The DMAC fetches the four-word descriptor (assuming that the memory is already set up with the descriptor chain) from the memory indicated by DDADR.

5.The four-word DMA descriptor, aligned on a 16-byte boundary in main memory, loads the following registers:

5-6	Intel® PXA255 Processor Developer’s Manual

Image 156

Intel PXA255 manual No-Descriptor Fetch Mode Channel State

Contents

Intel PXA255 Processor Intel PXA255 Processor Developer’s Manual Contents Power Manager General Configuration Register Pcfr Contents Expansion Card Interface Timing Diagrams and Parameters DMA 10-1 11-1 12.6 14.3 15.5 Figures BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF = 10-25 Tables Clocks Manager Register Summary Sxcnfg 10-6 10-8 12-26 15-7 Revision History Date Revision Description Xxiv Intel XScale Microarchitecture Features System Integration Features Clocks and Power Controllers Memory ControllerUniversal Serial Bus USB Client DMA Controller Dmac LCD Controller6 AC97 Controller Inter-IC Sound I2S Controller Synchronous Serial Protocol Controller Sspc Inter-Integrated Circuit I2C Bus Interface UnitGpio UARTs OS Timers Real-Time Clock RTCPulse-Width Modulator PWM Interrupt Control Introduction System Architecture Overview Intel XScale Microarchitecture Implementation Options Coprocessor 7 Register 4 Psfs Bit Coprocessor 14 Register 6 and 7- Clock and Power Management CPU Core Fault Register Bit DefinitionsCoprocessor 14 Registers 0-3 Performance Monitoring Coprocessor 15 Register 0 ID Register Definition Coprocessor 15 Register 1 P-Bit ID Bit DefinitionsPXA255 Processor ID Values ARM ID Jtag ID I/O Ordering SemaphoresInterrupts Reset Unit Sleep Mode Gpio Reset Watchdog Reset Hard ResetUSB ICP Internal Registers Selecting Peripherals vs. General Purpose I/O Power on Reset and Boot Operation Power ManagementPin List Processor Pin Types Pin & Signal Descriptions for the PXA255 Processor Sheet 1 Pin Name Type Signal Descriptions Reset State Sleep State Pin & Signal Descriptions for the PXA255 Processor Sheet 2 Pin & Signal Descriptions for the PXA255 Processor Sheet 3 Psktsel Pin & Signal Descriptions for the PXA255 Processor Sheet 4 Pin & Signal Descriptions for the PXA255 Processor Sheet 5 Pin & Signal Descriptions for the PXA255 Processor Sheet 6 Pin & Signal Descriptions for the PXA255 Processor Sheet 7 Pin & Signal Descriptions for the PXA255 Processor Sheet 8 BootselRtcclk Icocz Pwren Pin & Signal Descriptions for the PXA255 Processor Sheet 9 Pin Description Notes Sheet 1 Memory Map Pin Description Notes Sheet 2 Memory Map Part One From 0x80000000 to 0xFFFF Ffff Memory Map Part Two From 0x00000000 to 0x7FFF Ffff Unit Address Register Symbol Register Description System Architecture Register SummarySystem Architecture Register Address Summary Sheet 1 System Architecture Register Address Summary Sheet 2 System Architecture Register Address Summary Sheet 3 System Architecture Register Address Summary Sheet 4 System Architecture Register Address Summary Sheet 5 Unit System Architecture Register Address Summary Sheet 6 System Architecture Register Address Summary Sheet 7 Unit Address System Architecture Register Address Summary Sheet 8 System Architecture Register Address Summary Sheet 9 System Architecture Register Address Summary Sheet 10 System Architecture Register Address Summary Sheet 11 System Architecture Register Address Summary Sheet 12 Clocks and Power Manager Clock Manager Introduction Power Manager Introduction Clock Manager Retains Power in Sleep PWM SSPOST Ficp I2C MMC Core Phase Locked Loop 1 32.768 kHz Oscillator2 3.6864 MHz Oscillator 4 95.85 MHz Peripheral Phase Locked Loop 5 147.46 MHz Peripheral Phase Locked LoopCore PLL Output Frequencies for 3.6864 MHz Crystal Sdram Resets and Power Modes Hardware ResetClock Gating Watchdog Reset Gpio Reset Completing a Watchdog ResetInvoking Gpio Reset Behavior During Gpio Reset Run Mode Turbo ModeCompleting Gpio Reset Entering Turbo Mode Idle Mode Behavior in Turbo ModeExiting Turbo Mode Entering Idle Mode Behavior in Idle Mode Exiting Idle ModeFrequency Change Sequence Preparing for a Frequency Change Sequence Invoking the Frequency Change Sequence Behavior During the Frequency Change Sequence 8 33-MHz Idle Mode Completing the Frequency Change Sequence Entering 33-MHz Idle Mode Behavior in 33-MHz Idle Mode Sleep Mode Exiting 33-MHz Idle ModeSleep Mode External Voltage Regulator Requirements Preparing for Sleep Mode Entering Sleep Mode Clocks and Power Manager Behavior in Sleep Mode Exiting Sleep Mode Clocks and Power Manager Power Mode Summary Power Mode Entry Sequence TablePower Mode Exit Sequence Table Sheet 1 Idle Power Mode Exit Sequence Table Sheet 2 Power Manager Registers Power Mode Supply Source Module Turbo Run Power Manager Control Register Pmcr Pmcr Bit DefinitionsPmcr Idae Power Manager General Configuration Register Pcfr Pcfr Bit DefinitionsPcfr Opde Power Manager Wake-Up Enable Register Pwer Pwer Bit DefinitionsWertc Pwer Power Manager Rising-Edge Detect Enable Register Prer 10. Prer Bit Definitions0x40F00010 Prer Power Manager Falling-Edge Detect Enable Register Pfer 11. Pfer Bit Definitions0x40F00014 Pfer Power Manager Gpio Edge Detect Status Register Pedr 12. Pedr Bit Definitions0x40F00018 Pedr Power Manager Sleep Status Register Pssr 13. Pssr Bit Definitions Sheet 1Pssr RDH Power Manager Scratch Pad Register Pspr 13. Pssr Bit Definitions Sheet 214. Pspr Bit Definitions CPU VFS Power Manager Fast Sleep Walk-up Configuration Register Pmfw 15. Pmfw Register Bitmap and Bit Definitions 16. PGSR0 Bit Definitions 17. PGSR1 Bit DefinitionsPGSR0 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 Reset Controller Status Register Rcsr Bit Reset 0x40F0002818. PGSR2 Bit Definitions PGSR2 Core Clock Configuration Register Cccr Clocks Manager Registers19. Rcsr Bit Definitions Rcsr 20. Cccr Bit Definitions 0x41300000Bit Reserved Multiplier = Clock Enable Register Cken 21. Cken Bit Definitions Sheet 1 Description I2S Unit Clock Enable 21. Cken Bit Definitions Sheet 2CKEN8 CKEN5 Coprocessor 14 Clock and Power Management Oscillator Configuration Register Oscc22. Oscc Bit Definitions Core Clock Configuration Register Cclkcfg 23. Coprocessor 14 Clock and Power Management Summary24. Cclkcfg Bit Definitions Power Mode Register Pwrmode Power-On-Reset ConsiderationsPower Supply Connectivity External Hardware Considerations Clocks and Power Manager Register Summary Driving the Crystal Pins from an External Clock SourcePower Manager Register Summary Clocks Manager Register Locations 27. Power Manager Register Summary General-Purpose I/O Gpio Operation General-Purpose I/O Block Diagram Gpio Alternate Functions Gpio Alternate Functions Sheet 1 Gpio Alternate Functions Sheet 2 Gpio Alternate Functions Sheet 3 MMCCS0 ALTFN1OUTMbgnt ALTFN1OUT Gpio Register Definitions Gpio Alternate Functions Sheet 4Gpio Register Definitions Sheet 1 Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2 Gpio Register Definitions Sheet 2GPLR0 Bit Definitions GPLR0 Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2 GPLR1 Bit DefinitionsGPLR2 Bit Definitions GPLR1 GPDR0 Bit Definitions GPDR1 Bit DefinitionsGPDR2 Bit Definitions GPSR0 Bit Definitions 10. GPSR1 Bit DefinitionsGPSR0 PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 11. GPSR2 Bit Definitions 12. GPCR0 Bit Definitions13. GPCR1 Bit Definitions GPCR2 Bit Definitions GPCR2 15. GRER0 Bit Definitions 16. GRER1 Bit Definitions17. GRER2 Bit Definitions 18. GFER0 Bit Definitions 19. GFER1 Bit DefinitionsGFER2 Bit Definitions Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR2 21. GEDR0 Bit Definitions22. GEDR1 Bit Definitions GEDR2 Bit Definitions GEDR2 24. GAFR0L Bit Definitions 25. GAFR0U Bit DefinitionsGAFR0L AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0 26. GAFR1L Bit Definitions 27. GAFR1U Bit DefinitionsGAFR1L GAFR1U 28. GAFR2L Bit Definitions 29. GAFR2U Bit DefinitionsGAFR2L GAFR2U Interrupt Controller Interrupt Controller Operation Interrupt Controller Block Diagram Interrupt Controller Register Definitions Interrupt Controller Mask Register Icmr Interrupt Controller Level Register Iclr30. Icmr Bit Definitions Icmr Interrupt Controller Control Register Iccr 31. Iclr Bit Definitions32. Iccr Bit Definitions 33. Icip Bit Definitions 34. Icfp Bit Definitions Interrupt Controller Pending Register Icpr 35. Icpr Bit Definitions Sheet 1Icpr IS9 IS8 Network SSP Service Request Interrupt Pending 35. Icpr Bit Definitions Sheet 2IS14 IS13 IS12 IS11 IS10 IS16 35. Icpr Bit Definitions Sheet 3 36. List of First-Level Interrupts Sheet 1System Integration Unit Bit Position Source Unit Real-Time Clock RTC Real-Time Clock Operation36. List of First-Level Interrupts Sheet 2 RTC Register Definitions RTC Trim Register Rttr RTC Alarm Register Rtar Rttr Bit Definitions38. Rtar Bit Definitions RTC Counter Register Rcnr RTC Status Register Rtsr39. Rcnr Bit Definitions Rcnr Trim Procedure Oscillator Frequency Calibration40. Rtsr Bit Definitions Rttr Value Calculations Trim Example #1 Measured Value Has No Fractional ComponentTrim Example #2 Measured Value Has a Fractional Component Operating System OS Timer Maximum Error Calculation Versus RTC Accuracy Watchdog Timer Operation OS Timer Register DefinitionsOS Timer Match Register 0-3 OSMRx OS Timer Interrupt Enable Register Oier 41. OSMRx Bit Definitions42. Oier Bit Definitions OSMR3, OSMR2, OSMR1 OS Timer Watchdog Match Enable Register Ower OS Timer Count Register OscrOS Timer Status Register Ossr 43. Ower Bit Definitions 0x40A00014 Bit Reset ? ? ? ? ? ? ? ? Bits Pulse Width ModulatorPulse Width Modulator Operation Ossr Bit Definitions PWMn Block Diagram 1.1 Interdependencies Reset Sequence Power Management RequirementsRegister Descriptions PWM Control Registers PWMCTRLn PWM Duty Cycle Registers PWMDUTYn 46. PWMCTRLn Bit Definitions0x40B00000 Prescale PWM Period Control Register PWMPERVALn 47. PWMDUTYn Bit DefinitionsPWMDUTY0, PWMDUTY1 Fdcycle Dcycle Pulse Width Modulator Output Wave Example 48. PWMPERVALn Bit Definitions0x40B00008 System Integration Unit Register Summary Gpio Register Locations49. Gpio Register Addresses Sheet 1 OS Timer Register Locations Interrupt Controller Register LocationsReal-Time Clock Register Locations 52. OS Timer Register Addresses Sheet 2 Pulse Width Modulator Register Locations53. Pulse Width Modulator Register Addresses Dmac Block Diagram DMA Description Signal Descriptions DREQ10 and PREQ370 SignalsDmac Signal List Signal Signal Type To/From Definition In/Out Dmairq Signal DMA Channel Priority Scheme Channel Priority if all channels are running concurrently Channel Priority No-Descriptor Fetch Mode DMA DescriptorsPriority Schemes Examples DMA Channel Priority Descriptor Fetch Mode No-Descriptor Fetch Mode Channel State DMA Controller Channel States Servicing an Interrupt Read and Write Order Byte Transfer Order Trailing Bytes Little Endian Transfers Transferring Data Servicing Internal Peripherals Dcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg = Quick Reference for DMA Programming DMA Quick Reference for Internal Peripherals Sheet 1Dcmd Drcmr Servicing Companion Chips and External Peripherals DMA Quick Reference for Internal Peripherals Sheet 2Unit Function Fifo Address Width Burst Size Source DMA Controller Memory-to-Memory Moves Dmac Registers DMA Interrupt Register DintDMA Channel Control/Status Register DCSRx Dint Bit Definitions DCSRx Bit Definitions Sheet 1 RUNReqpend Stopstate Endintr Startintr Buserrintr Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCSRx Bit Definitions Sheet 2 DMA Request to Channel Map Registers DRCMRx DMA Descriptor Address Registers DDADRxDRCMRx Bit Definitions Chlnum DMA Source Address Registers DDADRx Bit DefinitionsDescriptor Address Stop DMA Target Address Registers DTADRx 10. DSADRx Bit DefinitionsSource Address Srcaddr DMA Command Registers DCMDx 11. DTADRx Bit DefinitionsTarget Address Trgaddr 12. DCMDx Bit Definitions Sheet 1 IncsrcaddrEndian Width Size 12. DCMDx Bit Definitions Sheet 2 EndianWidth Length Example 1. How to set up and start a channel Examples Struct longddadr longdsadr longdtadr shortlength shortdcmd DMA Controller Register Summary 13. DMA Controller Register Summary Sheet 1 13. DMA Controller Register Summary Sheet 2 13. DMA Controller Register Summary Sheet 3 13. DMA Controller Register Summary Sheet 4 13. DMA Controller Register Summary Sheet 5 Memory Controller Functional Description Sdram Interface Overview Static Memory Interface / Variable Latency I/O Interface Memory System Examples 3 16-Bit PC Card / Compact Flash Interface Sdram Memory System Example Static Memory System Example Memory Accesses Device TransactionsBus Operation Burst Size Words Bits Synchronous Dram Memory Interface Reads and WritesAborts and Nonexistent Memory Sdram Mdcnfg Register Mdcnfg Mdcnfg Bit Definitions Sheet 1 Mdcnfg Bit Definitions Sheet 2 Mdcnfg Bit Definitions Sheet 3 DNB2DADDR2 DLATCH2 Sdram Mode Register Set Configuration Register Mdmrs Mdmrs Bit Definitions Sheet 1 Low-Power Sdram Mode Register Set Configuration Register Mdmrs Bit Definitions Sheet 2 Sdram Mdrefr Register Mdrefr Mdmrslp Register Bit Definitions0X4800 Mdmrslp Mdrefr Bit Definitions Sheet 1 MdrefrAPD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PIN DRI Mdrefr Bit Definitions Sheet 2 0 1 0 0 1 * * 11 1 1 1 1 1 1 Fixed-Delay or Return-Clock Data Latching Mdrefr Bit Definitions Sheet 3APD Sdram Memory Options Sdram Addressing ModesSample Sdram Memory Size Options Number Chips Partition Size # Bits ‘0’1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32 MA2410 Col Data 2x13x10x16 ‘0’ # Bits External Address pins at Sdram RAS Time Not Valid illegal addressing combination MA24 MA23 MA20BA0 A10 MA24 BA1 BA0 A11 A10 Memory Controller Sdram Command Overview A12 11. Sdram Command Encoding 12. Sdram Mode Register Opcode TableSdram Waveforms Sdclk Data SDRAMreadsamebankdiffrow SDRAMwrite SDCLK1 SDCKE1 Synchronous Static Memory Configuration Register Sxcnfg Synchronous Static Memory Interface 13. Sxcnfg Bit Definitions Sheet 1 0x4800001CSxcnfg SXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2 Sxcnfg Bit Definitions Sheet 2 SXLATCH2SXRL2 SXCL2 SXEN2 SXLATCH0 13. Sxcnfg Bit Definitions Sheet 3 Smrom Memory Options Sxcnfg Bit Definitions Sheet 4SXCL0 SXEN0 Smrom Synchronous Static Memory Timing Diagrams 16. Sxmrs Bit DefinitionsSxmrs SXMRS2 Non-SDRAM Timing Sxmem Operation Sdclk Sdcke 17. Read Configuration Register Programming Values Memclk SDCLK0 Mdrefr Non-SDRAM Timing Flash Read Timing Diagram 12shows the burst-of-eight read timing diagram 4.2 K3 Synchronous StrataFlash Reset Asynchronous Static MemoryStatic Memory Interface Sram 19 -Bit Bus Write Access 20 -Bit Bus Write AccessData Size MA10 DQM30 Data Size MA0 DQM10 21 -Bit Byte Address Bits MA10 for Reads Based on DQM30 22 -Bit Byte Address Bit MA0 for Reads Based on DQM1023. SA-1111 Register Bit Definitions Asynchronous Static Memory Control Registers MSCx 24. MSC0/1/2 Bit Definitions Sheet 1 MSC0MSC1 MSC2 RRR1/3/5 RDN1/3/5 Reset RDF1/3/5 Bits Access Name24. MSC0/1/2 Bit Definitions Sheet 2 24. MSC0/1/2 Bit Definitions Sheet 3 Sram ROM Interface Timing Memory Clocks MSCxRTx DeviceNOE NWE NOE ROM Timing Diagrams and Parameters Clkmem RDN+1 Sram Timing Diagrams and Parameters Sram Interface Overview 20shows the timing for Sram writes Variable Latency I/O Vlio Interface Overview Variable Latency I/O Timing Diagrams and Parameters RDF+1+Waits RRR*2+1 RDF+1+Waits Flash Memory Timing Diagrams and Parameters Flash Memory Interface 23. Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes CMD Data Expansion Memory Timing Configuration Register 16-Bit PC Card/Compact Flash Interface26. MCMEM0/1 Bit Definitions MCMEM0 27. MCATT0/1 Bit Definitions 28. MCIO0/1 Bit DefinitionsMCATT0 MCATT1 29. Card Interface Command Assertion Code Table MCMEMxASST XASSTHOLD XASSTWAIT + Expansion Memory Configuration Register Mecr 30. Mecr Bit DefinitionMecr CIT NOS 3 16-Bit PC Card Overview 26 -Bit PC Card Memory Map 31. Common Memory Space Write Commands 32. Common Memory Space Read Commands33. Attribute Memory Space Write Commands 34. Attribute Memory Space Read Commands 37 -Bit I/O Space Write Commands nIOIS16 = 38 -Bit I/O Space Read Commands nIOIS16 =External Logic for 16-Bit PC Card Implementation DIR Socket Expansion Card Interface Timing Diagrams and Parameters 29 -Bit PC Card Memory or I/O 16-Bit Half-word Access 30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device Companion Chip Interface 31. Alternate Bus Master Mode 32. Variable Latency IO Alternate Bus Master Mode Gpio Reset NVDDFAULT/nBATTFAULT with Pmcridae DisabledNVDDFAULT/nBATTFAULT with Pmcridae Enabled Options and Settings for Boot Memory Alternate BootingBoot Time Defaults Bootdef Read-Only Register Bootdef 40. Bootdef Bitmap 41. Valid Boot Configurations Based on Processor TypeBootdef PKG Type Boot SEL Boot-Time Configurations Sxcnfg 34. Smrom Boot Time Configurations and Register Defaults Memory Interface Reset and Initialization SmromMdrefr 03CA 7FFF Hardware, Watchdog, or Sleep Reset Operation 42. Memory Controller Pin Reset ValuesPin Name PXA255 Processor Reset Value Memory Controller Gpio Reset Procedure Physical Address Symbol Register NameMemory Controller Register Summary 43. Memory Controller Register Summary Sheet 1 43. Memory Controller Register Summary Sheet 2 LCD Controller Features LCD Controller LCD Controller Block Diagram LCD Controller Operation Pin DescriptionsEnabling the Controller Pin Descriptions Resetting the Controller Detailed Module DescriptionsDisabling the Controller Input FIFOs Lookup Palette Temporal Modulated Energy Distribution Tmed Dithering Compare Range for Tmed Output FIFOs LCD Controller Pin Usage Pixel Data Pins LDDx 6 DMAPassive Display Timing Active Display Timing LCD External Palette and Frame Buffers External Palette Buffer External Frame Buffer Palette Buffer Format Bits Per Pixel Data Memory Organization 10 Bits Per Pixel Data Memory Organization Passive Mode Functional Timing FrameBufferSize = 12. Passive Mode Start-of-Frame Timing Vsync Hsync Lbias Register Descriptions Lfclk Vsync Llclk Hsync Lbias LCD Controller Control Register 0 LCCR0 LCD Controller LDD LCD Controller Data Pin Utilization Sheet 1 Single Passive Screen Portion Pins LCD Controller Data Pin Utilization Sheet 2 Reset X X X X X X X X X X X LCCR0 Bit Definitions Sheet 1LCCR0 0x44000000 Bit Reserved LCD Controller Control Register 1 LCCR1 LCCR0 Bit Definitions Sheet 2QDM DIS DPD PAS EFM IUM SFM LDM SDS CMS ENB LCD Controller LCD Controller Control Register 2 LCCR2 LCCR1 Bit DefinitionsBLW ELW HSW PPL BLW LCD Controller LCD Controller Control Register 3 LCCR3 LCCR2 Bit DefinitionsBFW EFW VSW LPP BFW LCD Controller LCD Controller Reset X X X X 0 0 0 LCCR3 Bit Definitions Sheet 10x4400000C Bit Reserved DPC BPP Reset X X X LCD Controller DMAFrame Descriptors LCCR3 Bit Definitions Sheet 2 LCD DMA Frame Descriptor Address Registers FDADRx LCD DMA Frame Source Address Registers FSADRxFDADRx Bit Definitions FDADR0 LCD DMA Frame ID Registers FIDRx FSADRx Bit DefinitionsFIDRx Bit Definitions LCD DMA Command Registers LDCMDx 10. LDCMDx Bit Definitions LDCMD0LDCMD1 PAL LCD DMA Frame Branch Registers FBRx 11. FBRx Bit DefinitionsBint BRA 0 0 0 0 X X 0 Bits Name Description LCD Controller Status Register Lcsr LCD Controller 0x44000038 Bit Reset X X Lcsr Bit Definitions Sheet 1X X EOF IUU IUL ABC BER SOF LDD LCD Controller Interrupt ID Register Liidr 12. Lcsr Bit Definitions Sheet 213. Liicr Bit Definitions Sint BS EOF QD OU IUU IUL ABC BER SOF LDD Tmed RGB Seed Register Trgbr 14. Trgbr Bit DefinitionsTBS TRS Tmed Control Register TCR LCD Controller Register Summary 15. TCR Bit Definitions16. LCD Controller Register Summary Sheet 1 16. LCD Controller Register Summary Sheet 2 LCD Controller Signal Description External Interface to Synchronous Serial PeripheralsExternal Interface to Codec Name Direction Description Data Formats Data TransferSerial Data Formats for Transfer to/from Peripherals SSP Format Details SPI Format Details Sspsclk SspsfrmSspsclk Sspsfrm MSB LSB Microwire Format Details Sspsclk Sspsfrm Ssptxd Ssprxd National Microwire* Frame Format Parallel Data Formats for Fifo Storage Using Programmed I/O Data Transfers Using DMA Data TransfersFifo Operation and Data Transfers Baud-Rate Generation SSP Serial Port Registers SSP Control Register 0 SSCR0 Data Size Select DSS SSCR0 Bit DefinitionsSSP Control Register 0 SSCR0 SCR Synchronous Serial Port Enable SSE Frame Format FRFExternal Clock Select ECS SSP Control Register 1 SSCR1 Serial Clock Rate SCRSSCR1 Bit Definitions Sheet 1 Receive Fifo Interrupt Enable RIE Transmit Fifo Interrupt Enable TIELoop Back Mode LBM SSCR1 Bit Definitions Sheet 2 Serial Clock Phase SPH Serial Clock Polarity SPOSspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Microwire Transmit Data Size Mwds Transmit Fifo Interrupt/DMA Threshold TFTReceive Fifo Interrupt/DMA Threshold RFT Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd SSP Data Register Ssdr TFT and RFT Values for DMA ServicingSsdr Bit Definitions SSP Status Register Sssr Transmit Fifo Not Full Flag TNF Sssr Bit DefinitionsRFL TFL ROR RFS TFS BSY RNE TNF RFL Transmit Fifo Service Request Flag TFS Receive Fifo Service Request Flag RFSReceive Fifo Not Empty Flag RNE SSP Busy Flag BSY SSP Controller Register Summary Receive Fifo Level RFLSSP Controller Register Summary Address Abbreviation Full Name Synchronous Serial Port Controller I2C Signal Description Signal Name Input/Output DescriptionSDA SCL I2C Bus Definitions 2C Device Definition Mode Description Operational Blocks2 I2C Bus Interface Modes Modes of Operation Start and Stop Bus States Start and Stop Bit DefinitionsStop Star Condition Start Condition No Start or Stop ConditionStop Condition ACK NAK StartACK ACK Stop NAK I2C Bus Operation Serial Clock Line SCL GenerationData and Addressing Management 3 I2C Acknowledge Addressing a Slave Device Polling Arbitration SCL Arbitration SDA Arbitration Arbitration Procedure of Two Masters 2C Master Mode Definition Action Operation Master OperationsMaster Transactions Sheet 1 Master Transactions Sheet 2 Slave Operations Master-Receiver Read from Slave-Transmitter 2C Slave Action Mode Definition Operation Slave Transactions General Call Address ACK StopNAK Stop General Call Address Second Byte Definitions Least Second Slave Mode Programming Examples Initialize UnitWrite n Bytes as a Slave Read n Bytes as a Slave Master Programming Examples Write 1 Byte as a Master Read 1 Byte as a Master Write 2 Bytes and Repeated Start Read 1 Byte as a Master Reset Conditions Read 2 Bytes as a Master Send Stop Using the AbortGlitch Suppression Logic Register Definitions 1 I2C Bus Monitor Register Ibmr2 I2C Data Buffer Register Idbr Ibmr Bit Definitions 3 I2C Control Register ICR Idbr Bit Definitions10. ICR Bit Definitions Sheet 1 40301690 Bit Reset Disable interrupt10. ICR Bit Definitions Sheet 2 Beie Irfie Iteie GCD IUE Receive mode 4 I2C Status Register ISR10. ICR Bit Definitions Sheet 3 11. ISR Bit Definitions Sheet 1 2C Status Register40301698 Bit BED SAD 5 I2C Slave Address Register Isar 11. ISR Bit Definitions Sheet 212. Isar Bit Definitions BED SAD Gcad IRF ITE ALD SSD IBB I2C Bus Interface Unit Feature List UARTs Bluetooth Uart Full Function UartStandard Uart Compatibility with Signal Descriptions Uart Signal Descriptions Sheet 1Name Type Description RXD Uart Signal Descriptions Sheet 2 Uart Operational DescriptionLSB MSB Reset Internal Register Descriptions Register Accessed Receive Buffer Register RBRUart Register Addresses as Offsets of a Base RBR Bit Definitions Transmit Holding Register THR Divisor Latch Registers DLL and DLHTHR Bit Definitions Interrupt Enable Register IER DLL Bit DefinitionsDLH Bit Definitions Interrupt Identification Register IIR IER Bit Definitions Interrupt Conditions IIR Bit Definitions Sheet 1Priority Level Interrupt origin FIFOES10 Interrupt ID Bits Interrupt SET/RESET Function FcrresetrfIIR Bit Definitions Sheet 2 10. Interrupt Identification Register Decode Sheet 1 Fifo Control Register FCR 10. Interrupt Identification Register Decode Sheet 211. FCR Bit Definitions Sheet 1 ITL Line Control Register LCR 11. FCR Bit Definitions Sheet 2 12. LCR Bit Definitions Base+0x0CUart Dlab Stkyp EPS PEN STB WLS1 WLS0 Line Status Register LSR 13. LSR Bit Definitions Sheet 1Fifoe Temt 13. LSR Bit Definitions Sheet 2 Tdrq 13. LSR Bit Definitions Sheet 3 Modem Control Register MCR 14. MCR Bit Definitions Sheet 1Uart Loop OUT2 OUT1 RTS DTR Modem Status Register MSR 14. MCR Bit Definitions Sheet 2Base+0x10 Modem Control Register 15. MSR Bit Definitions Fifo Interrupt Mode Operation Character Timeout Indication InterruptScratchpad Register SPR Receive Interrupt Fifo Polled Mode Operation DMA RequestsTransmit Interrupt Slow Infrared Asynchronous Interface Trailing Bytes in the Receive FifoInfrared Selection Register ISR Operation 17. ISR Bit Definitions IR Transmit and Receive Example Uart Register Summary 18. Ffuart Register Summary19. Btuart Register Summary Sheet 1 Dlab Bit Name Description 19. Btuart Register Summary Sheet 2 20. Stuart Register Summary Uart Register Differences 21. Flow Control Registers in Btuart and StuartBtmcr Btmsr Ficp Signal Description Ficp Operation 11.2.1 4PPM Modulation PPM Modulation Encodings Frame Format Address FieldControl Field Data Field CRC Field Baud Rate GenerationReceive Operation Transmit Operation Transmit and Receive FIFOs Trailing or Error Bytes in the Receive Fifo Ficp Register Definitions Ficp Control Register 0 ICCR0 ICCR0 Bit Definitions Sheet 1 ICCR0 Bit Definitions Sheet 2 TXETUS LBM Ficp Control Register 1 ICCR1 ICCR1 Bit Definitions Ficp Control Register 2 ICCR2 ICCR2 Bit Definitions Ficp Data Register Icdr Icrd Bit Definitions Ficp Status Register 0 ICSR0 ICSR0 Bit Definitions Sheet 1FRE RFS ICSR0 Bit Definitions Sheet 2 TUREIF Ficp Status Register 1 ICSR1 ICSR1 Bit Definitions Ficp Register Summary Ficp Register Summary USB Device Controller USB Overview Device Configuration Endpoint ConfigurationUSB Protocol IN/OUT Signalling Levels Bit EncodingUSB States Bus State UDC+/UDC- Pin Levels Field Formats Nrzi Bit Encoding Example IN, OUT, and Setup Token Packet Format Packet FormatsToken Packet Type Start of Frame Packet Type Transaction Formats Data Packet TypeHandshake Packet Type Bulk Transaction Type Isochronous Transaction Type Control Transaction TypeBulk Transaction Formats Isochronous Transaction Formats UDC Device Requests Interrupt Transaction Type10. Interrupt Transaction Formats Configuration 11. Host Device Request SummaryRequest Name Self-Powered Device UDC Hardware Connection When GPIOn and GPIOx are Different Pins When GPIOn and GPIOx are the Same Pin Bus-Powered Devices UDC OperationCase 1 EP0 Control Read Case 2 EP0 Control Read with a Premature Status Stage 12-14 Intel PXA255 Processor Developer’s Manual Case 4 EP0 No Data Command Software Enables the DMACase 5 EP1 Data Transmit BULK-IN Software Enables the EP1 Interrupt Case 6 EP2 Data Receive BULK-OUT Software Enables DMA Case 7 EP3 Data Transmit ISOCHRONOUS-INSoftware Allows the Megacell to Handle the Transaction Software Enables the EP3 Interrupt Software Enables the SOF InterruptCase 8 EP4 Data Receive ISOCHRONOUS-OUT Intel PXA255 Processor Developer’s Manual 12-19 Case 10 Reset Interrupt Case 9 EP5 Data Transmit INTERRUPT-IN UDC Register Definitions Case 11 Suspend InterruptCase 12 Resume Interrupt UDC Enable UDE UDC Control Register Udccr12. Udccr Bit Definitions Reset Interrupt Request Rstir Reset Interrupt Mask REMUDC Active UDA UDC Resume RSM ACK Control Mode ACK Response EnableUDC Control Function Register Udccfr 13. UDC Control Function Register UDC Endpoint 0 Control/Status Register UDCCS0 OUT Packet Ready OPRPacket Ready IPR 14. UDCCS0 Bit Definitions Device Remote Wakeup Feature Drwf Flush Tx Fifo FTFSent Stall SST Force Stall FST Setup Active SA Transmit Fifo Service TFSUDC Endpoint x Control/Status Register UDCCS1/6/11 15. UDCCS1/6/11 Bit Definitions Transmit Packet Complete TPC Transmit Underrun TURBit 6 Reserved UDC Endpoint x Control/Status Register UDCCS2/7/12 Transmit Short Packet TSP16. UDCCS2/7/12 Bit Definitions Receive Fifo Service RFS DMA Enable DMEReceive Packet Complete RPC Bit 2 Reserved UDC Endpoint x Control/Status Register UDCCS3/8/13 Receive Short Packet RSP17. UDCCS3/8/13 Bit Definitions UDC Endpoint x Control/Status Register UDCCS4/9/14 Bits 64 Reserved Receive Overflow ROF 18. UDCCS4/9/14 Bit Definitions UDC Endpoint x Control/Status Register UDCCS5/10/15 Bits 54 Reserved19. UDCCS5/10/15 Bit Definitions Sheet 1 19. UDCCS5/10/15 Bit Definitions Sheet 2 UDC Interrupt Control Register 0 UICR0 Interrupt Mask Endpoint x IMx, Where x is 0 through 20. UICR0 Bit DefinitionsUICR0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 Interrupt Mask Endpoint x IMx, where x is 8 through UDC Interrupt Control Register 1 UICR121. UICR1 Bit Definitions UICR1 UDC Status/Interrupt Register 0 USIR0 Endpoint 0 Interrupt Request IR0Endpoint 1 Interrupt Request IR1 22. USIR0 Bit Definitions Endpoint 2 Interrupt Request IR2 Endpoint 3 Interrupt Request IR3Endpoint 4 Interrupt Request IR4 Endpoint 5 Interrupt Request IR5 UDC Status/Interrupt Register 1 USIR1 Endpoint 8 Interrupt Request IR8Endpoint 9 Interrupt Request IR9 Endpoint 10 Interrupt Request IR10 UDC Frame Number High Register Ufnhr Isochronous Packet Error Endpoint 4 IPE4 Isochronous Packet Error Endpoint 9 IPE9UDC Frame Number MSB Fnmsb 24. Ufnhr Bit Definitions Isochronous Packet Error Endpoint 14 IPE14 UDC Frame Number Low Register UfnlrUDC Byte Count Register x UBCR2/4/7/9/12/14 Start of Frame Interrupt Mask SIM UDC Endpoint 0 Data Register UDDR0 Endpoint x Byte Count BC26. UBCR2/4/7/9/12/14 Bit Definitions UDC Endpoint x Data Register UDDR1/6/11 UDC Endpoint x Data Register UDDR2/7/1227. UDDR0 Bit Definitions 28. UDDR1/6/11 Bit Definitions UDC Endpoint x Data Register UDDR3/8/13 UDC Endpoint x Data Register UDDR4/9/1429. UDDR2/7/12 Bit Definitions 30. UDDR3/8/13 Bit Definitions USB Device Controller Register Summary UDC Endpoint x Data Register UDDR5/10/1531. UDDR4/9/14 Bit Definitions 32. UDDR5/10/15 Bit Definitions 33. USB Device Controller Register Summary Sheet 2 UfnhrUfnlr 33. USB Device Controller Register Summary Sheet 3 AC’97 Controller Unit Signal Configuration Steps Example AC-linkExternal Interface to CODECs Name Direction Description summary AC-link Digital Serial Interface Protocol Supported Data Stream Formats Sheet 1SDATAIN0 SDATAIN1 Channel Slots Comments AC-link Audio Output Frame Sdataout Supported Data Stream Formats Sheet 2Sync AC-link Audio Output Frame Slot 0 Tag Phase Slot 1 Command Address Port Slot 2 Command Data Port Slot 3 PCM Playback Left ChannelSlot 1 Bit Definitions Slot 2 Bit Definitions AC-link Audio Input Frame Sdatain Slot 4 PCM Playback Right ChannelSlot 5 Modem Line Codec Slots 6-11 Reserved Sync Slot 1 Status Address Port/SLOTREQ bits Input Slot 1 Bit Definitions Sheet 1Bit Description Slot 2 Status Data Port Slot 3 PCM Record Left ChannelSlot 4 PCM Record Right Channel Slot 5 Optional Modem Line Codec AC-link Low Power Mode Powering Down the AC-linkSlots 7-11 Reserved Slot 12 I/O Status Waking up the AC-link Wake up triggered by the Codec Cold AC’97 Reset Warm AC’97 ResetAcunit Operation Wake Up Triggered by the Acunit Initialization 13-16 Intel PXA255 Processor Developer’s Manual Operational Flow for Accessing Codec Registers Clocks and Sampling Frequencies Transmit Fifo Errors Receive Fifo ErrorsFIFOs Interrupts Registers Global Control Register GCR GCR Bit Definitions Sheet 1 Global Status Register GSR GCR Bit Definitions Sheet 2Warmrst Coldrst GSR Bit Definitions Sheet 1 Cdone SdoneRdcs Secres Prires SCR PCR Mint Point Piint PCM-Out Control Register Pocr GSR Bit Definitions Sheet 2Pocr Bit Definitions Sheet 1 PCM-In Control Register Picr Pocr Bit Definitions Sheet 210. Picr Bit Definitions PCM-Out Status Register Posr PCMIn Status Register Pisr11. Posr Bit Definitions 12. Pisr Bit Definitions Codec Access Register CAR PCM Data Register Pcdr13. CAR Bit Definitions 14. Pcdr Bit Definitions Mic-In Control Register Mccr Mic-In Status Register Mcsr15. Mccr Bit Definitions Mccr Register Mic-In Data Register Mcdr 16. Mcsr Bit Definitions17. Mcdr Bit Definitions Micindat Modem-Out Control Register Mocr Modem-In Control Register Micr18. Mocr Bit Definitions Mocr Register Modem-Out Status Register Mosr Modem-In Status Register Misr19. Micr Bit Definitions 20. Mosr Bit Definitions Modem Data Register Modr 21. Misr Bit Definitions22. Modr Bit Definitions Modemdat Accessing Codec Registers 11. Modem Transmit and Receive Operation 23. Address Mapping for Codec Registers Sheet 1 Processor Bit PhysicalAddress for a Primary Secondary Audio Codec Modem Codec 23. Address Mapping for Codec Registers Sheet 2 13.9 AC’97 Register Summary 24. Register Mapping Summary 13-36 Intel PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound I2S Controller GP32/SYSCLK GP29/SDATAIN Controller Operation Disabling and Enabling Audio Replay Disabling and Enabling Audio Record Transmit Fifo Errors Receive Fifo ErrorsSerial Audio Clocks and Sampling Frequencies Fifo and Memory Format 14.5.2 I2S and MSB-Justified Serial Audio FormatsSupported Sampling Frequencies Sysclk = Bitclk = I2S Data Formats 16 bits Registers Serial Audio Controller Global Control Register SACR0 Special purpose Fifo Read/Write function SACR0 Bit Definitions Suggested Tfth and Rfth for DMA servicing Fifo Write/Read tableTfth and Rfth Values for DMA Servicing Efwr Strf SACR1 Bit Definitions EnlbfDrpl Drec Serial Audio Clock Divider Register Sadiv SASR0 Bit DefinitionsRFL TFL Serial Audio Interrupt Clear Register Saicr Sadiv Bit DefinitionsSaicr Bit Definitions Serial Audio Interrupt Mask Register Saimr Serial Audio Data Register Sadr10. Saimr Bit Descriptions 11. Sadr Bit Descriptions Transmit and Receive Fifo Accesses Through the Sadr 14.8 I2S Controller Register Summary 12. Register Memory Map Address Register Description Paddr90 Name MultiMediaCard Controller Command Token Format MMC Data Token FormatSPI Data Token Format Mmcmd Mmdat MMC Controller Functional Description CRC Intel PXA255 Processor Developer’s Manual 15-5 Signal Description MMC Controller ResetMMC Signal Description Card Initialization Sequence MMC Mode Error Detection SPI Mode Clock Control Data FIFOs Response Data Fifo MmcresReceive Data FIFO, Mmcrxfifo Transmit Data FIFO, Mmctxfifo Card Communication Protocol DMA and Program I/O Basic, No Data, Command and Response Sequence Mmcclkrt Mmcspi Mmcresto Block Data Write Block Data Read Stream Data Write Busy Sequence Stream Data Read Enabling SPI Mode MultiMediaCard Controller OperationSPI Functionality Start and Stop Clock No Data Command and Response Sequence EraseSingle Data Block Write Single Block Read Multiple Block Write Multiple Block Read Stream Write Stream Read MMC Controller Registers Mmcstrpcl Register MMCStatus Register Mmcstat Mmcstrpcl Bit DefinitionsMmcstat Bit Definitions Sheet 1 Strpcl Mmcclkrt Register Mmcclkrt Mmcstat Bit Definitions Sheet 2 Mmcspi Register Mmcspi Mmcclk Bit DefinitionsMmcspi Bit Definitions Sheet 1 Mmccmdat Register Mmccmdat Mmcspi Bit Definitions Sheet 2Mmccmdat Bit Definitions Sheet 1 Mmcresto Register Mmcresto Mmccmdat Bit Definitions Sheet 210. Mmcresto Bit Definitions Mmcrdto Register Mmcrdto 11. Mmcrdto RegisterReadto Specifies the length of time before a data read time-out Mmcblklen Register Mmcblklen Mmcnob Register Mmcnob12. Mmcblklen Bit Definitions 13. Mmcnob Bit Definitions Mmcprtbuf Register Mmcprtbuf Mmcimask Register Mmcimask14. Mmcprtbuf Bit Definitions 15. Mmcimask Bit Definitions Sheet 1 Mmcireg Register Mmcireg 15. Mmcimask Bit Definitions Sheet 2Mmcimask Register MultiMediaCard Controller 4 3 2 1 16. Mmcireg Bit Definitions 18. Command Index Values Sheet 1 CMD Comm Mode Abbreviation IndexMmccmd Register Mmccmd 17. Mmccmd Register 18. Command Index Values Sheet 2 18. Command Index Values Sheet 3 Mmcargh Register MmcarghMmcargl Register Mmcargl 19. Mmcargh Bit Definitions Mmcres Fifo 21. MMCRES, Fifo Entry22. MMCRXFIFO, Fifo Entry Responsedata MultiMediaCard Controller Register Summary 23. MMCTXFIFO, Fifo Entry24. MMC Controller Registers Sheet 1 Writedata 24. MMC Controller Registers Sheet 2 Features Network SSP Serial Port Processor and DMA Fifo Access SSP Serial Port I/O SignalsOperation Trailing Bytes in the Receive Fifo Data Formats 16-4 Intel PXA255 Processor Developer’s Manual TI Synchronous Serial Protocol* Details SPI Protocol Details Serial Clock Phase SPH Motorola SPI* Frame Protocol multiple transfers 16-8 Intel PXA255 Processor Developer’s Manual Microwire* Protocol Details PSP Details Programmable Serial Protocol multiple transfers Programmable Serial Protocol PSP Parameters SspspscmodeSspspsfrmp Sspspstrtdly Hi-Z on Ssptxd 11. TI SSP with SSCRTTE=1 and SSCRTTELP=0 Motorola SPI Programmable Serial Protocol 16-16 Intel PXA255 Processor Developer’s Manual Fifo Operation Baud-Rate Generation 16-18 Intel PXA255 Processor Developer’s Manual SSCR0 Bit Definitions Sheet 1 SSCR0SCR SSE FRF DSS SSCR0 Bit Definitions Sheet 2 Edss SCR SSEData Size Select Edss DSS Ttelp TTE Ebcei Sclkdir Sfrmdir ScfrSSCR1 SPH SPO LBM TIE RIE SSP Programmable Serial Protocol Register Sspsp Sspsp Bit Definitions Sheet 1 SSP Time Out Register Ssto SSP Interrupt Test Register SsitrSspsp Bit Definitions Sheet 2 Ssto Bit Definitions Test Receive Fifo Service Request Trfs Test Transmit Fifo Service Request TtfsSsitr Bit Definitions Ssitr Sssr Bit Definitions Sheet 1 SssrBCE CSS TUR Tint Sssr Bit Definitions Sheet 2 Transmit Fifo Service Request Sssr Bit Definitions Sheet 3SSP Busy Receive Fifo not Empty Network SSP Serial Port Register Summary 10. Nssp Register Address MapSsdr Data TRANSMIT/RECEIVE Data 16-30 Intel PXA255 Processor Developer’s Manual Hardware Uart Hardware Uart Uart Signal Descriptions Operation 17-4 Intel PXA255 Processor Developer’s Manual Fifo Interrupt Mode Operation Fifo Polled Mode OperationCharacter Timeout Interrupt Receive Interrupt Fifo DMA Mode Operation DMA Receive Programming ErrorsDMA Error Handling Removing Trailing Bytes In DMA Mode Autoflow ControlAuto-Baud-Rate Detection 17-8 Intel PXA255 Processor Developer’s Manual Intel PXA255 Processor Developer’s Manual 17-9 Receive Buffer Register RBR Transmit Holding Register THRDivisor Latch Registers DLL and DLH Bit Reserved Byte Bits Name Description 318 Interrupt Enable Register IER Divisor Latch Register High DLH Bit DefinitionsDLL DLH Physical Address Interrupt Enable Register IER 0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description Interrupt Identification Register IIR IIRABL TOD IID NIP Priority Type Source Reset Control Interrupt Identification Register Decode Sheet 10x41600008 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 Fifo Control Register FCR Interrupt Identification Register Decode Sheet 210. FCR Bit Definitions Sheet 1 Receive Fifo Occupancy Register for 10. FCR Bit Definitions Sheet 211. for Bit Definitions Auto-Baud Control Register ABR Auto-Baud Count Register ACR12. ABR Bit Definitions ABT Line Control Register LCR 13. ACR Bit Definitions14. LCR Bit Definitions Sheet 1 ACR Line Status Register LSR 14. LCR Bit Definitions Sheet 2Line Control Register LCR PXA255 Processor Hardware Uart Dlab Stkyp EPS PEN STB WLS 15. LSR Bit Definitions Sheet 1 0x41600014 Bit? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits Modem Control Register MCR 15. LSR Bit Definitions Sheet 2Line Status Register LSR PXA255 Processor Hardware Uart 0 0 0 0 Bits Name Description 0x41600010 Bit Reset ? ? ? ? ? ? ? Bits 16. MCR Bit Definitions Sheet 1Physical Address Modem Control Register MCR AFE Modem Status Register MSR 16. MCR Bit Definitions Sheet 217. MSR Bit Definitions Sheet 1 Scratchpad Register SCR Infrared Selection Register ISR17. MSR Bit Definitions Sheet 2 18. SCR Bit Definitions Hardware Uart Register Summary 19. ISR Bit Definitions20. Hwuart Register Locations Sheet 1 Rxpl Txpl Xmode Rcveir Xmitir 20. Hwuart Register Locations Sheet 2 Intel PXA255 Processor Developer’s Manual 17-27