LCD Controller

Figure 7-14. Passive Mode Pixel Clock and Data Pin Timing

L_FCLK

L_LCLK

PCP = 0

L_PCLK

LDD[3:0]

Pixels 0 .. 3

Pixels 4 .. 7

Pixels 8 .. 11

Pixels 12 .. 15

Pixels 16 .. 19

PCP - Pixel Clock Polarity

0 - Pixels sampled from data pins on rising edge of clock

1 - Pixels sampled from data pins on falling edge of clock

For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical.

Figure 7-15. Active Mode Timing

 

ENB set to 1

 

 

 

VSW = 0

 

 

L_FCLK

VSP = 0

 

 

(VSYNC)

 

 

 

 

HSW = 1

BFW = 1

 

L_LCLK

HSP = 0

 

 

(HSYNC)

 

 

 

 

 

L_BIAS

 

 

 

(OE)

 

 

 

 

 

BLW = 0

ELW = 0

L_PCLK

PCP = 0

 

 

 

PPL = 7

 

 

 

 

LDD[15:0] Line 0 Data Line 1 Data Line 2 Data

ENB - LCD Enable

HSP - Horizontal Sync Polarity

0

- LCD is disabled

0

- Horizontal sync clock is active high, inactive low

1

- LCD is enabled

1

- Horizontal sync clock is active low, inactive high

VSP - Vertical Sync Polarity

PCP - Pixel Clock Polarity

0

- Vertical sync clock is active high, inactive low

0

- Pixels sampled from data pins on rising edge of clock

1

- Vertical sync clock is active low, inactive high

1

- Pixels sampled from data pins on falling edge of clock

For PCP = 1 the L_PCLK waveform is inverted, but the timing is identical.

VSW = Vertical Sync Pulse Width - 1

HSW = Horizontal Sync Pulse Width - 1

BFW = Beginning-of-Frame Horizontal Sync Clock Wait Count

BLW = Beginning-of-Line Pixel Clock Wait Count - 1

ELW = End-of-Line Pixel Clock Wait Count - 1

PPL = Pixels Per Line - 1

7-16

Intel® PXA255 Processor Developer’s Manual

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Image 280
Intel PXA255 manual Vsync, Hsync Lbias