DMA Controller

Wait for Request: Channel is waiting for a request before it starts to transfer the data.

Transfer Data: Channel is transferring data.

Channel Error: Channel has an error. It remains in the stopped state until software clears the error condition, re-initializes the channel, and writes a 1 to the DCSR[RUN] bit. See Section 5.3.1 and Section 5.3.2 for details.

Stopped: Channel is stopped.

Figure 5-3and Figure 5-4show the progression from state to state.

5.1.6Read and Write Order

The DMAC does not ensure the order of programmed I/O reads and writes made from the processor to the I/O devices (including the on-chip I/O devices). Software must ensure the order.

The DMAC ensures that all memory references made by a single DMA data stream are presented to main memory in the order in which they were made. The descriptor fetches occurs between the data blocks. This allows self-modifying DMA descriptor chains to function correctly (see Example 4 on page 5-27). It also allows schemes in which a DMA stream writes data blocks followed by status blocks and schemes in which another DMA stream (probably from the processor) polls the same field in the status block.

The DMAC ensures that data is not retained in per-channel buffers between descriptors. When a descriptor is completely processed, any read data that is buffered in the channel is discarded and any write data that is buffered in the channel is sent to memory (although it may not be there yet). The DMA interrupt is not posted until the descriptor is completely processed.

5.1.7Byte Transfer Order

The DCMD[ENDIAN] bit indicates the byte ordering in a word when data is read from or written to memory. Refer to Figure 5-5for details. The DCMD[ENDIAN} bit must be set to 0, which is little endian transfers.

Figure 5-5shows the order which data is transferred as determined by the DCMD[ENDIAN] and DCMD[SIZE] bits.

If data is being transferred from an internal device to memory, DCMD[ENDIAN] is set to a 0, and DCMD[SIZE] is set to a 1, the memory receives the data in the following order:

1.Byte[0]

2.Byte[1]

3.Byte[2]

4.Byte[3]

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Read and Write Order, Byte Transfer Order