General Call Address Second Byte Definitions

I2C Bus Interface Unit

The I2C unit supports sending and receiving general call address transfers on the I2C bus. When software sends a general call message from the I2C unit, it must set the ICR[GCD] bit to prevent the I2C unit from responding as a slave. If the ICR[GCD] is not set, the I2C bus enters an indeterminate state.

If the I2C unit acts as a slave and receives a general call address while the ICR[GCD] bit is clear, it:

•Sets the ISR[GCAD] bit

•Sets the ISR[SAD] bit

•Interrupts the processor (if the interrupt is enabled)

If the I2C unit receives a general call address and the ICR[GCD] bit is set, it ignores the general call address.

Figure 9-14. General Call Address

START

00000000

ACK

Second Byte

ACK

Data

ACK

Data

ACK

STOP

Byte

First Byte

Second Byte

N Bytes + ACK

Least Significant Bit of Master Address

Defines Transaction

Master to Slave

Slave to Master

Table 9-7. General Call Address Second Byte Definitions

Least	Second
Significant	Second
Significant	Byte	Definition
Bit of Second	Byte	Definition
Bit of Second	Value
Byte (B)	Value
Byte (B)

0	0x06	2-byte transaction in which the second byte tells the slave to reset and store this
0	0x06	value in the programmable part of its address.
		value in the programmable part of its address.

0	0x04	2-byte transaction in which the second byte tells the slave to store this value in
0	0x04	the programmable part of its address. No reset.
		the programmable part of its address. No reset.

0	0x00	Not allowed as a second byte

NOTE: Other values are not fixed and must be ignored.

Software must ensure that the I2C unit is not busy before it asserts a reset. Software must also ensure that the I2C bus is idle when the unit is enabled after reset. When directed to reset, the I2C unit, except for ISAR, returns to the default reset condition. ISAR is not affected by a reset.

When B=1, the sequence is a hardware general call and is not supported by the I2C unit. Refer to the The I2C-Bus Specification for information on hardware general calls.

I2C 10-bit addresses and CBUS compatibility are not supported.

Intel® PXA255 Processor Developer’s Manual

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Page 347

Image 347

Intel PXA255 manual General Call Address Second Byte Definitions, Least Second

Contents

Intel PXA255 Processor Intel PXA255 Processor Developer’s Manual Contents Power Manager General Configuration Register Pcfr Contents Expansion Card Interface Timing Diagrams and Parameters DMA 10-1 11-1 12.6 14.3 15.5 Figures BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF = 10-25 Tables Clocks Manager Register Summary Sxcnfg 10-6 10-8 12-26 15-7 Date Revision Description Revision History Xxiv System Integration Features Intel XScale Microarchitecture Features Universal Serial Bus USB Client Clocks and Power ControllersMemory Controller Inter-IC Sound I2S Controller DMA Controller DmacLCD Controller 6 AC97 Controller UARTs Synchronous Serial Protocol Controller SspcInter-Integrated Circuit I2C Bus Interface Unit Gpio Interrupt Control OS TimersReal-Time Clock RTC Pulse-Width Modulator PWM Introduction Overview System Architecture Coprocessor 7 Register 4 Psfs Bit Intel XScale Microarchitecture Implementation Options Coprocessor 15 Register 0 ID Register Definition Coprocessor 14 Register 6 and 7- Clock and Power ManagementCPU Core Fault Register Bit Definitions Coprocessor 14 Registers 0-3 Performance Monitoring ARM ID Jtag ID Coprocessor 15 Register 1 P-BitID Bit Definitions PXA255 Processor ID Values Interrupts I/O OrderingSemaphores ICP ResetUnit Sleep Mode Gpio Reset Watchdog Reset Hard Reset USB Selecting Peripherals vs. General Purpose I/O Internal Registers Processor Pin Types Power on Reset and Boot OperationPower Management Pin List Pin Name Type Signal Descriptions Reset State Sleep State Pin & Signal Descriptions for the PXA255 Processor Sheet 1 Pin & Signal Descriptions for the PXA255 Processor Sheet 2 Psktsel Pin & Signal Descriptions for the PXA255 Processor Sheet 3 Pin & Signal Descriptions for the PXA255 Processor Sheet 4 Pin & Signal Descriptions for the PXA255 Processor Sheet 5 Pin & Signal Descriptions for the PXA255 Processor Sheet 6 Pin & Signal Descriptions for the PXA255 Processor Sheet 7 Pwren Pin & Signal Descriptions for the PXA255 Processor Sheet 8Bootsel Rtcclk Icocz Pin Description Notes Sheet 1 Pin & Signal Descriptions for the PXA255 Processor Sheet 9 Pin Description Notes Sheet 2 Memory Map Memory Map Part One From 0x80000000 to 0xFFFF Ffff Memory Map Part Two From 0x00000000 to 0x7FFF Ffff System Architecture Register Address Summary Sheet 1 Unit Address Register Symbol Register DescriptionSystem Architecture Register Summary System Architecture Register Address Summary Sheet 2 System Architecture Register Address Summary Sheet 3 System Architecture Register Address Summary Sheet 4 Unit System Architecture Register Address Summary Sheet 5 System Architecture Register Address Summary Sheet 6 Unit Address System Architecture Register Address Summary Sheet 7 System Architecture Register Address Summary Sheet 8 System Architecture Register Address Summary Sheet 9 System Architecture Register Address Summary Sheet 10 System Architecture Register Address Summary Sheet 11 System Architecture Register Address Summary Sheet 12 Clock Manager Introduction Clocks and Power Manager Clock Manager Power Manager Introduction Ficp I2C MMC Retains Power in SleepPWM SSP OST 2 3.6864 MHz Oscillator Core Phase Locked Loop1 32.768 kHz Oscillator Sdram 4 95.85 MHz Peripheral Phase Locked Loop5 147.46 MHz Peripheral Phase Locked Loop Core PLL Output Frequencies for 3.6864 MHz Crystal Clock Gating Resets and Power ModesHardware Reset Watchdog Reset Behavior During Gpio Reset Gpio ResetCompleting a Watchdog Reset Invoking Gpio Reset Entering Turbo Mode Run ModeTurbo Mode Completing Gpio Reset Entering Idle Mode Idle ModeBehavior in Turbo Mode Exiting Turbo Mode Preparing for a Frequency Change Sequence Behavior in Idle ModeExiting Idle Mode Frequency Change Sequence Behavior During the Frequency Change Sequence Invoking the Frequency Change Sequence Completing the Frequency Change Sequence 8 33-MHz Idle Mode Behavior in 33-MHz Idle Mode Entering 33-MHz Idle Mode Sleep Mode External Voltage Regulator Requirements Sleep ModeExiting 33-MHz Idle Mode Entering Sleep Mode Preparing for Sleep Mode Clocks and Power Manager Exiting Sleep Mode Behavior in Sleep Mode Clocks and Power Manager Idle Power Mode SummaryPower Mode Entry Sequence Table Power Mode Exit Sequence Table Sheet 1 Power Mode Exit Sequence Table Sheet 2 Power Mode Supply Source Module Turbo Run Power Manager Registers Idae Power Manager Control Register PmcrPmcr Bit Definitions Pmcr Opde Power Manager General Configuration Register PcfrPcfr Bit Definitions Pcfr Pwer Power Manager Wake-Up Enable Register PwerPwer Bit Definitions Wertc Prer Power Manager Rising-Edge Detect Enable Register Prer10. Prer Bit Definitions 0x40F00010 Pfer Power Manager Falling-Edge Detect Enable Register Pfer11. Pfer Bit Definitions 0x40F00014 Pedr Power Manager Gpio Edge Detect Status Register Pedr12. Pedr Bit Definitions 0x40F00018 RDH Power Manager Sleep Status Register Pssr13. Pssr Bit Definitions Sheet 1 Pssr CPU VFS Power Manager Scratch Pad Register Pspr13. Pssr Bit Definitions Sheet 2 14. Pspr Bit Definitions 15. Pmfw Register Bitmap and Bit Definitions Power Manager Fast Sleep Walk-up Configuration Register Pmfw SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 16. PGSR0 Bit Definitions17. PGSR1 Bit Definitions PGSR0 PGSR2 Reset Controller Status Register RcsrBit Reset 0x40F00028 18. PGSR2 Bit Definitions Rcsr Core Clock Configuration Register CccrClocks Manager Registers 19. Rcsr Bit Definitions Multiplier = 20. Cccr Bit Definitions0x41300000 Bit Reserved 21. Cken Bit Definitions Sheet 1 Clock Enable Register Cken CKEN5 Description I2S Unit Clock Enable21. Cken Bit Definitions Sheet 2 CKEN8 22. Oscc Bit Definitions Coprocessor 14 Clock and Power ManagementOscillator Configuration Register Oscc 24. Cclkcfg Bit Definitions Core Clock Configuration Register Cclkcfg23. Coprocessor 14 Clock and Power Management Summary External Hardware Considerations Power Mode Register PwrmodePower-On-Reset Considerations Power Supply Connectivity Clocks Manager Register Locations Clocks and Power Manager Register SummaryDriving the Crystal Pins from an External Clock Source Power Manager Register Summary 27. Power Manager Register Summary Gpio Operation General-Purpose I/O Gpio Alternate Functions General-Purpose I/O Block Diagram Gpio Alternate Functions Sheet 1 Gpio Alternate Functions Sheet 2 Mbgnt ALTFN1OUT Gpio Alternate Functions Sheet 3MMCCS0 ALTFN1OUT Gpio Register Definitions Sheet 1 Gpio Register DefinitionsGpio Alternate Functions Sheet 4 GPLR0 Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2Gpio Register Definitions Sheet 2 GPLR0 Bit Definitions GPLR1 Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2GPLR1 Bit Definitions GPLR2 Bit Definitions GPDR2 Bit Definitions GPDR0 Bit DefinitionsGPDR1 Bit Definitions PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 GPSR0 Bit Definitions10. GPSR1 Bit Definitions GPSR0 13. GPCR1 Bit Definitions 11. GPSR2 Bit Definitions12. GPCR0 Bit Definitions GPCR2 GPCR2 Bit Definitions 17. GRER2 Bit Definitions 15. GRER0 Bit Definitions16. GRER1 Bit Definitions GFER2 Bit Definitions 18. GFER0 Bit Definitions19. GFER1 Bit Definitions 22. GEDR1 Bit Definitions Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR221. GEDR0 Bit Definitions GEDR2 GEDR2 Bit Definitions AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0 24. GAFR0L Bit Definitions25. GAFR0U Bit Definitions GAFR0L GAFR1U 26. GAFR1L Bit Definitions27. GAFR1U Bit Definitions GAFR1L GAFR2U 28. GAFR2L Bit Definitions29. GAFR2U Bit Definitions GAFR2L Interrupt Controller Operation Interrupt Controller Interrupt Controller Register Definitions Interrupt Controller Block Diagram Icmr Interrupt Controller Mask Register IcmrInterrupt Controller Level Register Iclr 30. Icmr Bit Definitions 32. Iccr Bit Definitions Interrupt Controller Control Register Iccr31. Iclr Bit Definitions 34. Icfp Bit Definitions 33. Icip Bit Definitions IS9 IS8 Interrupt Controller Pending Register Icpr35. Icpr Bit Definitions Sheet 1 Icpr IS16 Network SSP Service Request Interrupt Pending35. Icpr Bit Definitions Sheet 2 IS14 IS13 IS12 IS11 IS10 Bit Position Source Unit 35. Icpr Bit Definitions Sheet 336. List of First-Level Interrupts Sheet 1 System Integration Unit 36. List of First-Level Interrupts Sheet 2 Real-Time Clock RTCReal-Time Clock Operation RTC Trim Register Rttr RTC Register Definitions 38. Rtar Bit Definitions RTC Alarm Register RtarRttr Bit Definitions Rcnr RTC Counter Register RcnrRTC Status Register Rtsr 39. Rcnr Bit Definitions 40. Rtsr Bit Definitions Trim ProcedureOscillator Frequency Calibration Trim Example #2 Measured Value Has a Fractional Component Rttr Value CalculationsTrim Example #1 Measured Value Has No Fractional Component Maximum Error Calculation Versus RTC Accuracy Operating System OS Timer OS Timer Match Register 0-3 OSMRx Watchdog Timer OperationOS Timer Register Definitions OSMR3, OSMR2, OSMR1 OS Timer Interrupt Enable Register Oier41. OSMRx Bit Definitions 42. Oier Bit Definitions 43. Ower Bit Definitions OS Timer Watchdog Match Enable Register OwerOS Timer Count Register Oscr OS Timer Status Register Ossr Ossr Bit Definitions 0x40A00014 Bit Reset ? ? ? ? ? ? ? ? BitsPulse Width Modulator Pulse Width Modulator Operation 1.1 Interdependencies PWMn Block Diagram PWM Control Registers PWMCTRLn Reset SequencePower Management Requirements Register Descriptions Prescale PWM Duty Cycle Registers PWMDUTYn46. PWMCTRLn Bit Definitions 0x40B00000 Fdcycle Dcycle PWM Period Control Register PWMPERVALn47. PWMDUTYn Bit Definitions PWMDUTY0, PWMDUTY1 0x40B00008 Pulse Width Modulator Output Wave Example48. PWMPERVALn Bit Definitions 49. Gpio Register Addresses Sheet 1 System Integration Unit Register SummaryGpio Register Locations Real-Time Clock Register Locations OS Timer Register LocationsInterrupt Controller Register Locations 53. Pulse Width Modulator Register Addresses 52. OS Timer Register Addresses Sheet 2Pulse Width Modulator Register Locations DMA Description Dmac Block Diagram Signal Signal Type To/From Definition In/Out Signal DescriptionsDREQ10 and PREQ370 Signals Dmac Signal List DMA Channel Priority Scheme Dmairq Signal Channel Priority Channel Priority if all channels are running concurrently DMA Channel Priority No-Descriptor Fetch ModeDMA Descriptors Priority Schemes Examples No-Descriptor Fetch Mode Channel State Descriptor Fetch Mode DMA Controller Servicing an Interrupt Channel States Byte Transfer Order Read and Write Order Little Endian Transfers Trailing Bytes Servicing Internal Peripherals Transferring Data Dcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg = Drcmr Quick Reference for DMA ProgrammingDMA Quick Reference for Internal Peripherals Sheet 1 Dcmd Burst Size Source Servicing Companion Chips and External PeripheralsDMA Quick Reference for Internal Peripherals Sheet 2 Unit Function Fifo Address Width DMA Controller Memory-to-Memory Moves Dint Bit Definitions Dmac RegistersDMA Interrupt Register Dint DMA Channel Control/Status Register DCSRx Stopstate Endintr Startintr Buserrintr DCSRx Bit Definitions Sheet 1RUN Reqpend DCSRx Bit Definitions Sheet 2 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Chlnum DMA Request to Channel Map Registers DRCMRxDMA Descriptor Address Registers DDADRx DRCMRx Bit Definitions Stop DMA Source Address RegistersDDADRx Bit Definitions Descriptor Address Srcaddr DMA Target Address Registers DTADRx10. DSADRx Bit Definitions Source Address Trgaddr DMA Command Registers DCMDx11. DTADRx Bit Definitions Target Address Size 12. DCMDx Bit Definitions Sheet 1Incsrcaddr Endian Width Length 12. DCMDx Bit Definitions Sheet 2Endian Width Examples Example 1. How to set up and start a channel Struct longddadr longdsadr longdtadr shortlength shortdcmd 13. DMA Controller Register Summary Sheet 1 DMA Controller Register Summary 13. DMA Controller Register Summary Sheet 2 13. DMA Controller Register Summary Sheet 3 13. DMA Controller Register Summary Sheet 4 13. DMA Controller Register Summary Sheet 5 Memory Controller Sdram Interface Overview Functional Description Static Memory Interface / Variable Latency I/O Interface 3 16-Bit PC Card / Compact Flash Interface Memory System Examples Sdram Memory System Example Static Memory System Example Words Bits Memory AccessesDevice Transactions Bus Operation Burst Size Sdram Mdcnfg Register Mdcnfg Synchronous Dram Memory InterfaceReads and Writes Aborts and Nonexistent Memory Mdcnfg Bit Definitions Sheet 1 Mdcnfg Bit Definitions Sheet 2 DLATCH2 Mdcnfg Bit Definitions Sheet 3DNB2 DADDR2 Mdmrs Bit Definitions Sheet 1 Sdram Mode Register Set Configuration Register Mdmrs Mdmrs Bit Definitions Sheet 2 Low-Power Sdram Mode Register Set Configuration Register Mdmrslp Sdram Mdrefr Register MdrefrMdmrslp Register Bit Definitions 0X4800 DRI Mdrefr Bit Definitions Sheet 1Mdrefr APD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PIN 1 1 1 1 1 1 1 Mdrefr Bit Definitions Sheet 20 1 0 0 1 * * 1 APD Fixed-Delay or Return-Clock Data LatchingMdrefr Bit Definitions Sheet 3 Number Chips Partition Size Sdram Memory OptionsSdram Addressing Modes Sample Sdram Memory Size Options 1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32 # Bits‘0’ Col Data MA2410 2x13x10x16 ‘0’ Not Valid illegal addressing combination # Bits External Address pins at Sdram RAS Time A10 MA24 MA23MA20 BA0 BA1 BA0 MA24 A11 A10 Memory Controller A12 Sdram Command Overview Sdram Waveforms 11. Sdram Command Encoding12. Sdram Mode Register Opcode Table Data Sdclk SDRAMreadsamebankdiffrow SDCLK1 SDCKE1 SDRAMwrite Synchronous Static Memory Interface Synchronous Static Memory Configuration Register Sxcnfg SXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2 13. Sxcnfg Bit Definitions Sheet 10x4800001C Sxcnfg SXLATCH0 Sxcnfg Bit Definitions Sheet 2SXLATCH2 SXRL2 SXCL2 SXEN2 13. Sxcnfg Bit Definitions Sheet 3 SXEN0 Smrom Memory OptionsSxcnfg Bit Definitions Sheet 4 SXCL0 Smrom SXMRS2 Synchronous Static Memory Timing Diagrams16. Sxmrs Bit Definitions Sxmrs Sdclk Sdcke Non-SDRAM Timing Sxmem Operation Memclk SDCLK0 Mdrefr 17. Read Configuration Register Programming Values 12shows the burst-of-eight read timing diagram Non-SDRAM Timing Flash Read Timing Diagram Static Memory Interface 4.2 K3 Synchronous StrataFlash ResetAsynchronous Static Memory Sram Data Size MA0 DQM10 19 -Bit Bus Write Access20 -Bit Bus Write Access Data Size MA10 DQM30 23. SA-1111 Register Bit Definitions 21 -Bit Byte Address Bits MA10 for Reads Based on DQM3022 -Bit Byte Address Bit MA0 for Reads Based on DQM10 Asynchronous Static Memory Control Registers MSCx MSC2 24. MSC0/1/2 Bit Definitions Sheet 1MSC0 MSC1 24. MSC0/1/2 Bit Definitions Sheet 2 RRR1/3/5 RDN1/3/5 Reset RDF1/3/5Bits Access Name Sram 24. MSC0/1/2 Bit Definitions Sheet 3 NWE NOE ROM InterfaceTiming Memory Clocks MSCxRTx Device NOE Clkmem ROM Timing Diagrams and Parameters RDN+1 Sram Interface Overview Sram Timing Diagrams and Parameters 20shows the timing for Sram writes Variable Latency I/O Vlio Interface Overview RDF+1+Waits RRR*2+1 Variable Latency I/O Timing Diagrams and Parameters RDF+1+Waits Flash Memory Interface Flash Memory Timing Diagrams and Parameters CMD Data 23. Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes MCMEM0 Expansion Memory Timing Configuration Register16-Bit PC Card/Compact Flash Interface 26. MCMEM0/1 Bit Definitions MCATT1 27. MCATT0/1 Bit Definitions28. MCIO0/1 Bit Definitions MCATT0 MCMEMxASST XASSTHOLD XASSTWAIT + 29. Card Interface Command Assertion Code Table CIT NOS Expansion Memory Configuration Register Mecr30. Mecr Bit Definition Mecr 26 -Bit PC Card Memory Map 3 16-Bit PC Card Overview 34. Attribute Memory Space Read Commands 31. Common Memory Space Write Commands32. Common Memory Space Read Commands 33. Attribute Memory Space Write Commands External Logic for 16-Bit PC Card Implementation 37 -Bit I/O Space Write Commands nIOIS16 =38 -Bit I/O Space Read Commands nIOIS16 = DIR Socket 29 -Bit PC Card Memory or I/O 16-Bit Half-word Access Expansion Card Interface Timing Diagrams and Parameters Companion Chip Interface 30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device 32. Variable Latency IO 31. Alternate Bus Master Mode Alternate Bus Master Mode NVDDFAULT/nBATTFAULT with Pmcridae Enabled Gpio ResetNVDDFAULT/nBATTFAULT with Pmcridae Disabled Bootdef Read-Only Register Bootdef Options and Settings for Boot MemoryAlternate Booting Boot Time Defaults PKG Type Boot SEL 40. Bootdef Bitmap41. Valid Boot Configurations Based on Processor Type Bootdef Sxcnfg Boot-Time Configurations 34. Smrom Boot Time Configurations and Register Defaults Mdrefr 03CA 7FFF Memory Interface Reset and InitializationSmrom Pin Name PXA255 Processor Reset Value Hardware, Watchdog, or Sleep Reset Operation42. Memory Controller Pin Reset Values Memory Controller 43. Memory Controller Register Summary Sheet 1 Gpio Reset ProcedurePhysical Address Symbol Register Name Memory Controller Register Summary 43. Memory Controller Register Summary Sheet 2 LCD Controller LCD Controller Features LCD Controller Block Diagram Pin Descriptions LCD Controller OperationPin Descriptions Enabling the Controller Input FIFOs Resetting the ControllerDetailed Module Descriptions Disabling the Controller Temporal Modulated Energy Distribution Tmed Dithering Lookup Palette Compare Range for Tmed LCD Controller Pin Usage Output FIFOs Active Display Timing Pixel Data Pins LDDx6 DMA Passive Display Timing External Palette Buffer LCD External Palette and Frame Buffers Palette Buffer Format External Frame Buffer Bits Per Pixel Data Memory Organization 10 Bits Per Pixel Data Memory Organization Passive Mode FrameBufferSize = Functional Timing 12. Passive Mode Start-of-Frame Timing Hsync Lbias Vsync Lfclk Vsync Llclk Hsync Lbias Register Descriptions LCD Controller Control Register 0 LCCR0 LCD Controller LDD LCD Controller Data Pin Utilization Sheet 1 LCD Controller Data Pin Utilization Sheet 2 Single Passive Screen Portion Pins 0x44000000 Bit Reserved Reset X X X X X X X X X X XLCCR0 Bit Definitions Sheet 1 LCCR0 PAS EFM IUM SFM LDM SDS CMS ENB LCD Controller Control Register 1 LCCR1LCCR0 Bit Definitions Sheet 2 QDM DIS DPD LCD Controller BLW LCD Controller Control Register 2 LCCR2LCCR1 Bit Definitions BLW ELW HSW PPL LCD Controller BFW LCD Controller Control Register 3 LCCR3LCCR2 Bit Definitions BFW EFW VSW LPP LCD Controller LCD Controller DPC BPP Reset X X X X 0 0 0LCCR3 Bit Definitions Sheet 1 0x4400000C Bit Reserved LCCR3 Bit Definitions Sheet 2 Reset X X XLCD Controller DMA Frame Descriptors FDADR0 LCD DMA Frame Descriptor Address Registers FDADRxLCD DMA Frame Source Address Registers FSADRx FDADRx Bit Definitions FIDRx Bit Definitions LCD DMA Frame ID Registers FIDRxFSADRx Bit Definitions LCD DMA Command Registers LDCMDx PAL 10. LDCMDx Bit DefinitionsLDCMD0 LDCMD1 0 0 0 0 X X 0 Bits Name Description LCD DMA Frame Branch Registers FBRx11. FBRx Bit Definitions Bint BRA LCD Controller Status Register Lcsr LCD Controller EOF IUU IUL ABC BER SOF LDD 0x44000038 Bit Reset X XLcsr Bit Definitions Sheet 1 X X Sint BS EOF QD OU IUU IUL ABC BER SOF LDD LCD Controller Interrupt ID Register Liidr12. Lcsr Bit Definitions Sheet 2 13. Liicr Bit Definitions TRS Tmed RGB Seed Register Trgbr14. Trgbr Bit Definitions TBS Tmed Control Register TCR 16. LCD Controller Register Summary Sheet 1 LCD Controller Register Summary15. TCR Bit Definitions 16. LCD Controller Register Summary Sheet 2 LCD Controller Name Direction Description Signal DescriptionExternal Interface to Synchronous Serial Peripherals External Interface to Codec Serial Data Formats for Transfer to/from Peripherals Data FormatsData Transfer SSP Format Details LSB SPI Format DetailsSspsclk Sspsfrm Sspsclk Sspsfrm MSB Sspsclk Sspsfrm Ssptxd Ssprxd Microwire Format Details Parallel Data Formats for Fifo Storage National Microwire* Frame Format Baud-Rate Generation Using Programmed I/O Data TransfersUsing DMA Data Transfers Fifo Operation and Data Transfers SSP Control Register 0 SSCR0 SSP Serial Port Registers SCR Data Size Select DSSSSCR0 Bit Definitions SSP Control Register 0 SSCR0 External Clock Select ECS Synchronous Serial Port Enable SSEFrame Format FRF SSCR1 Bit Definitions Sheet 1 SSP Control Register 1 SSCR1Serial Clock Rate SCR SSCR1 Bit Definitions Sheet 2 Receive Fifo Interrupt Enable RIETransmit Fifo Interrupt Enable TIE Loop Back Mode LBM Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Serial Clock Phase SPHSerial Clock Polarity SPO Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Microwire Transmit Data Size MwdsTransmit Fifo Interrupt/DMA Threshold TFT Receive Fifo Interrupt/DMA Threshold RFT Ssdr Bit Definitions SSP Data Register SsdrTFT and RFT Values for DMA Servicing SSP Status Register Sssr RFL Transmit Fifo Not Full Flag TNFSssr Bit Definitions RFL TFL ROR RFS TFS BSY RNE TNF SSP Busy Flag BSY Transmit Fifo Service Request Flag TFSReceive Fifo Service Request Flag RFS Receive Fifo Not Empty Flag RNE Address Abbreviation Full Name SSP Controller Register SummaryReceive Fifo Level RFL SSP Controller Register Summary Synchronous Serial Port Controller SCL I2C Signal DescriptionSignal Name Input/Output Description SDA 2C Device Definition I2C Bus Definitions Modes of Operation Mode DescriptionOperational Blocks 2 I2C Bus Interface Modes Condition Start and Stop Bus StatesStart and Stop Bit Definitions Stop Star Stop Condition Start ConditionNo Start or Stop Condition ACK Stop NAK ACK NAKStart ACK Data and Addressing Management I2C Bus OperationSerial Clock Line SCL Generation Addressing a Slave Device 3 I2C Acknowledge Arbitration Polling SDA Arbitration SCL Arbitration Arbitration Procedure of Two Masters Master Transactions Sheet 1 2C Master Mode Definition Action OperationMaster Operations Master Transactions Sheet 2 Master-Receiver Read from Slave-Transmitter Slave Operations Slave Transactions 2C Slave Action Mode Definition Operation NAK Stop General Call AddressACK Stop Least Second General Call Address Second Byte Definitions Read n Bytes as a Slave Slave Mode Programming ExamplesInitialize Unit Write n Bytes as a Slave Write 1 Byte as a Master Master Programming Examples Write 2 Bytes and Repeated Start Read 1 Byte as a Master Read 1 Byte as a Master Glitch Suppression Logic Reset ConditionsRead 2 Bytes as a Master Send Stop Using the Abort Ibmr Bit Definitions Register Definitions1 I2C Bus Monitor Register Ibmr 2 I2C Data Buffer Register Idbr 10. ICR Bit Definitions Sheet 1 3 I2C Control Register ICRIdbr Bit Definitions Beie Irfie Iteie GCD IUE 40301690 Bit ResetDisable interrupt 10. ICR Bit Definitions Sheet 2 10. ICR Bit Definitions Sheet 3 Receive mode4 I2C Status Register ISR BED SAD 11. ISR Bit Definitions Sheet 12C Status Register 40301698 Bit BED SAD Gcad IRF ITE ALD SSD IBB 5 I2C Slave Address Register Isar11. ISR Bit Definitions Sheet 2 12. Isar Bit Definitions I2C Bus Interface Unit UARTs Feature List Compatibility with Bluetooth UartFull Function Uart Standard Uart RXD Signal DescriptionsUart Signal Descriptions Sheet 1 Name Type Description LSB MSB Uart Signal Descriptions Sheet 2Uart Operational Description Internal Register Descriptions Reset RBR Bit Definitions Register AccessedReceive Buffer Register RBR Uart Register Addresses as Offsets of a Base THR Bit Definitions Transmit Holding Register THRDivisor Latch Registers DLL and DLH DLH Bit Definitions Interrupt Enable Register IERDLL Bit Definitions IER Bit Definitions Interrupt Identification Register IIR FIFOES10 Interrupt ConditionsIIR Bit Definitions Sheet 1 Priority Level Interrupt origin 10. Interrupt Identification Register Decode Sheet 1 Interrupt ID Bits Interrupt SET/RESET FunctionFcrresetrf IIR Bit Definitions Sheet 2 ITL Fifo Control Register FCR10. Interrupt Identification Register Decode Sheet 2 11. FCR Bit Definitions Sheet 1 11. FCR Bit Definitions Sheet 2 Line Control Register LCR Uart Dlab Stkyp EPS PEN STB WLS1 WLS0 12. LCR Bit DefinitionsBase+0x0C Temt Line Status Register LSR13. LSR Bit Definitions Sheet 1 Fifoe Tdrq 13. LSR Bit Definitions Sheet 2 13. LSR Bit Definitions Sheet 3 Loop OUT2 OUT1 RTS DTR Modem Control Register MCR14. MCR Bit Definitions Sheet 1 Uart Base+0x10 Modem Control Register Modem Status Register MSR14. MCR Bit Definitions Sheet 2 15. MSR Bit Definitions Receive Interrupt Fifo Interrupt Mode OperationCharacter Timeout Indication Interrupt Scratchpad Register SPR Transmit Interrupt Fifo Polled Mode OperationDMA Requests Infrared Selection Register ISR Slow Infrared Asynchronous InterfaceTrailing Bytes in the Receive Fifo 17. ISR Bit Definitions Operation IR Transmit and Receive Example Dlab Bit Name Description Uart Register Summary18. Ffuart Register Summary 19. Btuart Register Summary Sheet 1 20. Stuart Register Summary 19. Btuart Register Summary Sheet 2 Btmsr Uart Register Differences21. Flow Control Registers in Btuart and Stuart Btmcr Ficp Operation Ficp Signal Description PPM Modulation Encodings 11.2.1 4PPM Modulation Data Field Frame FormatAddress Field Control Field Receive Operation CRC FieldBaud Rate Generation Transmit Operation Transmit and Receive FIFOs Ficp Register Definitions Trailing or Error Bytes in the Receive Fifo ICCR0 Bit Definitions Sheet 1 Ficp Control Register 0 ICCR0 LBM ICCR0 Bit Definitions Sheet 2TXE TUS ICCR1 Bit Definitions Ficp Control Register 1 ICCR1 ICCR2 Bit Definitions Ficp Control Register 2 ICCR2 Icrd Bit Definitions Ficp Data Register Icdr RFS Ficp Status Register 0 ICSR0ICSR0 Bit Definitions Sheet 1 FRE EIF ICSR0 Bit Definitions Sheet 2TUR ICSR1 Bit Definitions Ficp Status Register 1 ICSR1 Ficp Register Summary Ficp Register Summary USB Overview USB Device Controller IN/OUT Device ConfigurationEndpoint Configuration USB Protocol Bus State UDC+/UDC- Pin Levels Signalling LevelsBit Encoding USB States Nrzi Bit Encoding Example Field Formats Start of Frame Packet Type IN, OUT, and Setup Token Packet FormatPacket Formats Token Packet Type Bulk Transaction Type Transaction FormatsData Packet Type Handshake Packet Type Isochronous Transaction Formats Isochronous Transaction TypeControl Transaction Type Bulk Transaction Formats 10. Interrupt Transaction Formats UDC Device RequestsInterrupt Transaction Type Request Name Configuration11. Host Device Request Summary UDC Hardware Connection Self-Powered Device When GPIOn and GPIOx are the Same Pin When GPIOn and GPIOx are Different Pins Case 1 EP0 Control Read Bus-Powered DevicesUDC Operation Case 2 EP0 Control Read with a Premature Status Stage 12-14 Intel PXA255 Processor Developer’s Manual Case 5 EP1 Data Transmit BULK-IN Case 4 EP0 No Data CommandSoftware Enables the DMA Case 6 EP2 Data Receive BULK-OUT Software Enables the EP1 Interrupt Software Allows the Megacell to Handle the Transaction Software Enables DMACase 7 EP3 Data Transmit ISOCHRONOUS-IN Case 8 EP4 Data Receive ISOCHRONOUS-OUT Software Enables the EP3 InterruptSoftware Enables the SOF Interrupt Intel PXA255 Processor Developer’s Manual 12-19 Case 9 EP5 Data Transmit INTERRUPT-IN Case 10 Reset Interrupt Case 12 Resume Interrupt UDC Register DefinitionsCase 11 Suspend Interrupt 12. Udccr Bit Definitions UDC Enable UDEUDC Control Register Udccr UDC Resume RSM Reset Interrupt Request RstirReset Interrupt Mask REM UDC Active UDA 13. UDC Control Function Register ACK Control ModeACK Response Enable UDC Control Function Register Udccfr 14. UDCCS0 Bit Definitions UDC Endpoint 0 Control/Status Register UDCCS0OUT Packet Ready OPR Packet Ready IPR Force Stall FST Device Remote Wakeup Feature DrwfFlush Tx Fifo FTF Sent Stall SST 15. UDCCS1/6/11 Bit Definitions Setup Active SATransmit Fifo Service TFS UDC Endpoint x Control/Status Register UDCCS1/6/11 Bit 6 Reserved Transmit Packet Complete TPCTransmit Underrun TUR 16. UDCCS2/7/12 Bit Definitions UDC Endpoint x Control/Status Register UDCCS2/7/12Transmit Short Packet TSP Bit 2 Reserved Receive Fifo Service RFSDMA Enable DME Receive Packet Complete RPC 17. UDCCS3/8/13 Bit Definitions UDC Endpoint x Control/Status Register UDCCS3/8/13Receive Short Packet RSP Bits 64 Reserved UDC Endpoint x Control/Status Register UDCCS4/9/14 18. UDCCS4/9/14 Bit Definitions Receive Overflow ROF 19. UDCCS5/10/15 Bit Definitions Sheet 1 UDC Endpoint x Control/Status Register UDCCS5/10/15Bits 54 Reserved 19. UDCCS5/10/15 Bit Definitions Sheet 2 UDC Interrupt Control Register 0 UICR0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 Interrupt Mask Endpoint x IMx, Where x is 0 through20. UICR0 Bit Definitions UICR0 UICR1 Interrupt Mask Endpoint x IMx, where x is 8 throughUDC Interrupt Control Register 1 UICR1 21. UICR1 Bit Definitions 22. USIR0 Bit Definitions UDC Status/Interrupt Register 0 USIR0Endpoint 0 Interrupt Request IR0 Endpoint 1 Interrupt Request IR1 Endpoint 5 Interrupt Request IR5 Endpoint 2 Interrupt Request IR2Endpoint 3 Interrupt Request IR3 Endpoint 4 Interrupt Request IR4 Endpoint 10 Interrupt Request IR10 UDC Status/Interrupt Register 1 USIR1Endpoint 8 Interrupt Request IR8 Endpoint 9 Interrupt Request IR9 UDC Frame Number High Register Ufnhr 24. Ufnhr Bit Definitions Isochronous Packet Error Endpoint 4 IPE4Isochronous Packet Error Endpoint 9 IPE9 UDC Frame Number MSB Fnmsb Start of Frame Interrupt Mask SIM Isochronous Packet Error Endpoint 14 IPE14UDC Frame Number Low Register Ufnlr UDC Byte Count Register x UBCR2/4/7/9/12/14 26. UBCR2/4/7/9/12/14 Bit Definitions UDC Endpoint 0 Data Register UDDR0Endpoint x Byte Count BC 28. UDDR1/6/11 Bit Definitions UDC Endpoint x Data Register UDDR1/6/11UDC Endpoint x Data Register UDDR2/7/12 27. UDDR0 Bit Definitions 30. UDDR3/8/13 Bit Definitions UDC Endpoint x Data Register UDDR3/8/13UDC Endpoint x Data Register UDDR4/9/14 29. UDDR2/7/12 Bit Definitions 32. UDDR5/10/15 Bit Definitions USB Device Controller Register SummaryUDC Endpoint x Data Register UDDR5/10/15 31. UDDR4/9/14 Bit Definitions Ufnlr 33. USB Device Controller Register Summary Sheet 2Ufnhr 33. USB Device Controller Register Summary Sheet 3 AC’97 Controller Unit Name Direction Description summary Signal Configuration StepsExample AC-link External Interface to CODECs Channel Slots Comments AC-link Digital Serial Interface ProtocolSupported Data Stream Formats Sheet 1 SDATAIN0 SDATAIN1 Sync AC-link Audio Output Frame SdataoutSupported Data Stream Formats Sheet 2 AC-link Audio Output Frame Slot 1 Command Address Port Slot 0 Tag Phase Slot 2 Bit Definitions Slot 2 Command Data PortSlot 3 PCM Playback Left Channel Slot 1 Bit Definitions Slots 6-11 Reserved AC-link Audio Input Frame SdatainSlot 4 PCM Playback Right Channel Slot 5 Modem Line Codec Sync Bit Description Slot 1 Status Address Port/SLOTREQ bitsInput Slot 1 Bit Definitions Sheet 1 Slot 5 Optional Modem Line Codec Slot 2 Status Data PortSlot 3 PCM Record Left Channel Slot 4 PCM Record Right Channel Slot 12 I/O Status AC-link Low Power ModePowering Down the AC-link Slots 7-11 Reserved Wake up triggered by the Codec Waking up the AC-link Wake Up Triggered by the Acunit Cold AC’97 ResetWarm AC’97 Reset Acunit Operation Initialization 13-16 Intel PXA255 Processor Developer’s Manual Clocks and Sampling Frequencies Operational Flow for Accessing Codec Registers FIFOs Transmit Fifo ErrorsReceive Fifo Errors Registers Interrupts GCR Bit Definitions Sheet 1 Global Control Register GCR Coldrst Global Status Register GSRGCR Bit Definitions Sheet 2 Warmrst Secres Prires SCR PCR Mint Point Piint GSR Bit Definitions Sheet 1Cdone Sdone Rdcs Pocr Bit Definitions Sheet 1 PCM-Out Control Register PocrGSR Bit Definitions Sheet 2 10. Picr Bit Definitions PCM-In Control Register PicrPocr Bit Definitions Sheet 2 12. Pisr Bit Definitions PCM-Out Status Register PosrPCMIn Status Register Pisr 11. Posr Bit Definitions 14. Pcdr Bit Definitions Codec Access Register CARPCM Data Register Pcdr 13. CAR Bit Definitions Mccr Register Mic-In Control Register MccrMic-In Status Register Mcsr 15. Mccr Bit Definitions Micindat Mic-In Data Register Mcdr16. Mcsr Bit Definitions 17. Mcdr Bit Definitions Mocr Register Modem-Out Control Register MocrModem-In Control Register Micr 18. Mocr Bit Definitions 20. Mosr Bit Definitions Modem-Out Status Register MosrModem-In Status Register Misr 19. Micr Bit Definitions Modemdat Modem Data Register Modr21. Misr Bit Definitions 22. Modr Bit Definitions 11. Modem Transmit and Receive Operation Accessing Codec Registers Address for a Primary Secondary Audio Codec Modem Codec 23. Address Mapping for Codec Registers Sheet 1Processor Bit Physical 23. Address Mapping for Codec Registers Sheet 2 24. Register Mapping Summary 13.9 AC’97 Register Summary 13-36 Intel PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound I2S Controller GP29/SDATAIN GP32/SYSCLK Controller Operation Disabling and Enabling Audio Record Disabling and Enabling Audio Replay Serial Audio Clocks and Sampling Frequencies Transmit Fifo ErrorsReceive Fifo Errors Sysclk = Bitclk = Fifo and Memory Format14.5.2 I2S and MSB-Justified Serial Audio Formats Supported Sampling Frequencies I2S Data Formats 16 bits Serial Audio Controller Global Control Register SACR0 Registers SACR0 Bit Definitions Special purpose Fifo Read/Write function Efwr Strf Suggested Tfth and Rfth for DMA servicingFifo Write/Read table Tfth and Rfth Values for DMA Servicing Drec SACR1 Bit DefinitionsEnlbf Drpl TFL Serial Audio Clock Divider Register SadivSASR0 Bit Definitions RFL Saicr Bit Definitions Serial Audio Interrupt Clear Register SaicrSadiv Bit Definitions 11. Sadr Bit Descriptions Serial Audio Interrupt Mask Register SaimrSerial Audio Data Register Sadr 10. Saimr Bit Descriptions 14.8 I2S Controller Register Summary Transmit and Receive Fifo Accesses Through the Sadr Address Register Description Paddr90 Name 12. Register Memory Map MultiMediaCard Controller SPI Data Token Format Command Token FormatMMC Data Token Format Mmdat Mmcmd CRC MMC Controller Functional Description Intel PXA255 Processor Developer’s Manual 15-5 Card Initialization Sequence Signal DescriptionMMC Controller Reset MMC Signal Description MMC Mode SPI Mode Error Detection Clock Control Receive Data FIFO, Mmcrxfifo Data FIFOsResponse Data Fifo Mmcres Transmit Data FIFO, Mmctxfifo DMA and Program I/O Card Communication Protocol Mmcclkrt Mmcspi Mmcresto Basic, No Data, Command and Response Sequence Block Data Write Stream Data Write Block Data Read Stream Data Read Busy Sequence Start and Stop Clock Enabling SPI ModeMultiMediaCard Controller Operation SPI Functionality Single Data Block Write No Data Command and Response SequenceErase Single Block Read Multiple Block Read Multiple Block Write Stream Read Stream Write Mmcstrpcl Register MMC Controller Registers Strpcl MMCStatus Register MmcstatMmcstrpcl Bit Definitions Mmcstat Bit Definitions Sheet 1 Mmcstat Bit Definitions Sheet 2 Mmcclkrt Register Mmcclkrt Mmcspi Bit Definitions Sheet 1 Mmcspi Register MmcspiMmcclk Bit Definitions Mmccmdat Bit Definitions Sheet 1 Mmccmdat Register MmccmdatMmcspi Bit Definitions Sheet 2 10. Mmcresto Bit Definitions Mmcresto Register MmcrestoMmccmdat Bit Definitions Sheet 2 Specifies the length of time before a data read time-out Mmcrdto Register Mmcrdto11. Mmcrdto Register Readto 13. Mmcnob Bit Definitions Mmcblklen Register MmcblklenMmcnob Register Mmcnob 12. Mmcblklen Bit Definitions 15. Mmcimask Bit Definitions Sheet 1 Mmcprtbuf Register MmcprtbufMmcimask Register Mmcimask 14. Mmcprtbuf Bit Definitions 4 3 2 1 Mmcireg Register Mmcireg15. Mmcimask Bit Definitions Sheet 2 Mmcimask Register MultiMediaCard Controller 16. Mmcireg Bit Definitions 17. Mmccmd Register 18. Command Index Values Sheet 1CMD Comm Mode Abbreviation Index Mmccmd Register Mmccmd 18. Command Index Values Sheet 2 19. Mmcargh Bit Definitions 18. Command Index Values Sheet 3Mmcargh Register Mmcargh Mmcargl Register Mmcargl Responsedata Mmcres Fifo21. MMCRES, Fifo Entry 22. MMCRXFIFO, Fifo Entry Writedata MultiMediaCard Controller Register Summary23. MMCTXFIFO, Fifo Entry 24. MMC Controller Registers Sheet 1 24. MMC Controller Registers Sheet 2 Network SSP Serial Port Features Operation Processor and DMA Fifo AccessSSP Serial Port I/O Signals Data Formats Trailing Bytes in the Receive Fifo 16-4 Intel PXA255 Processor Developer’s Manual TI Synchronous Serial Protocol* Details SPI Protocol Details Motorola SPI* Frame Protocol multiple transfers Serial Clock Phase SPH 16-8 Intel PXA255 Processor Developer’s Manual Microwire* Protocol Details PSP Details Programmable Serial Protocol multiple transfers Sspspstrtdly Programmable Serial Protocol PSP ParametersSspspscmode Sspspsfrmp 11. TI SSP with SSCRTTE=1 and SSCRTTELP=0 Hi-Z on Ssptxd Motorola SPI Programmable Serial Protocol 16-16 Intel PXA255 Processor Developer’s Manual Baud-Rate Generation Fifo Operation 16-18 Intel PXA255 Processor Developer’s Manual FRF DSS SSCR0 Bit Definitions Sheet 1SSCR0 SCR SSE Edss DSS SSCR0 Bit Definitions Sheet 2Edss SCR SSE Data Size Select SPH SPO LBM TIE RIE Ttelp TTE EbceiSclkdir Sfrmdir Scfr SSCR1 SSP Programmable Serial Protocol Register Sspsp Sspsp Bit Definitions Sheet 1 Ssto Bit Definitions SSP Time Out Register SstoSSP Interrupt Test Register Ssitr Sspsp Bit Definitions Sheet 2 Ssitr Test Receive Fifo Service Request TrfsTest Transmit Fifo Service Request Ttfs Ssitr Bit Definitions Tint Sssr Bit Definitions Sheet 1Sssr BCE CSS TUR Sssr Bit Definitions Sheet 2 Receive Fifo not Empty Transmit Fifo Service RequestSssr Bit Definitions Sheet 3 SSP Busy Data TRANSMIT/RECEIVE Data Network SSP Serial Port Register Summary10. Nssp Register Address Map Ssdr 16-30 Intel PXA255 Processor Developer’s Manual Hardware Uart Hardware Uart Operation Uart Signal Descriptions 17-4 Intel PXA255 Processor Developer’s Manual Receive Interrupt Fifo Interrupt Mode OperationFifo Polled Mode Operation Character Timeout Interrupt DMA Error Handling Fifo DMA Mode OperationDMA Receive Programming Errors Auto-Baud-Rate Detection Removing Trailing Bytes In DMA ModeAutoflow Control 17-8 Intel PXA255 Processor Developer’s Manual Intel PXA255 Processor Developer’s Manual 17-9 Bit Reserved Byte Bits Name Description 318 Receive Buffer Register RBRTransmit Holding Register THR Divisor Latch Registers DLL and DLH DLH Interrupt Enable Register IERDivisor Latch Register High DLH Bit Definitions DLL ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description Physical Address Interrupt Enable Register IER0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name NIP Interrupt Identification Register IIRIIR ABL TOD IID ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 Priority Type Source Reset ControlInterrupt Identification Register Decode Sheet 1 0x41600008 10. FCR Bit Definitions Sheet 1 Fifo Control Register FCRInterrupt Identification Register Decode Sheet 2 11. for Bit Definitions Receive Fifo Occupancy Register for10. FCR Bit Definitions Sheet 2 ABT Auto-Baud Control Register ABRAuto-Baud Count Register ACR 12. ABR Bit Definitions ACR Line Control Register LCR13. ACR Bit Definitions 14. LCR Bit Definitions Sheet 1 Dlab Stkyp EPS PEN STB WLS Line Status Register LSR14. LCR Bit Definitions Sheet 2 Line Control Register LCR PXA255 Processor Hardware Uart ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits 15. LSR Bit Definitions Sheet 10x41600014 Bit 0 0 0 0 Bits Name Description Modem Control Register MCR15. LSR Bit Definitions Sheet 2 Line Status Register LSR PXA255 Processor Hardware Uart AFE 0x41600010 Bit Reset ? ? ? ? ? ? ? Bits16. MCR Bit Definitions Sheet 1 Physical Address Modem Control Register MCR 17. MSR Bit Definitions Sheet 1 Modem Status Register MSR16. MCR Bit Definitions Sheet 2 18. SCR Bit Definitions Scratchpad Register SCRInfrared Selection Register ISR 17. MSR Bit Definitions Sheet 2 Rxpl Txpl Xmode Rcveir Xmitir Hardware Uart Register Summary19. ISR Bit Definitions 20. Hwuart Register Locations Sheet 1 20. Hwuart Register Locations Sheet 2 Intel PXA255 Processor Developer’s Manual 17-27