Memory Controller

Table 6-18. Frequency Code Configuration Values Based on Clock Speed (Sheet 2 of 2)

MEMCLK

SDCLK0

 

MDREFR:

 

Valid

Corresponding

 

 

Frequency

Frequency

Frequency

 

K0DB2

 

CAS Latencies

 

 

Configurations

 

 

 

 

 

 

 

 

 

 

 

 

 

133

66

1

 

5 / 6

 

6 / 7

 

 

 

 

 

 

 

147

Not supported

 

 

 

 

 

 

 

 

 

 

 

 

166

Not supported

 

 

 

 

 

 

 

 

 

 

 

 

6.6.4.1Non-SDRAM Timing Flash Read Timing Diagram

Figure 6-12shows the burst-of-eight read timing diagram.

Figure 6-13. Burst-of-Eight Synchronous Flash Timing Diagram (non-divide-by-2 mode)

0ns

50ns

100ns

150ns

200ns

SDCLK[0]

MA[19:0] nCS[0]

nADV(nSDCAS) nOE nWE

MD[31:0]

DQM[3:0]

byte address

SXCNFG[CL]

0000

This diagram is for SXCNFG:CL = "100" (CAS Latency = 5) (Frequency Code Configuration = 4)

In Figure 6-13, the following timing parameters apply:

nADV asserted time = 1 MEMCLK

MA, nCS setup to nADV asserted = 1 MEMCLK

nADV deasserted to nOE asserted = Code - 2 MEMCLKs

Intel® PXA255 Processor Developer’s Manual

6-41

Page 223
Image 223
Intel PXA255 manual Non-SDRAM Timing Flash Read Timing Diagram, 12shows the burst-of-eight read timing diagram