Intel PXA255 manual SSP Serial Port Registers, SSP Control Register 0 SSCR0

Synchronous Serial Port Controller

8.7SSP Serial Port Registers

The SSPC has five registers: two control, one data, one status, and one “reserved” register:

•The SSPC Control Registers (SSCR0 and SSCR1) are used to program the baud rate, data length, frame format, data transfer mechanism, and port enabling. They also control the FIFO “fullness” threshold that triggers an interrupt. These registers must be written before the SSP is enabled after reset and must only be changed when SSP is disabled.

•The SSPC Data Register (SSDR) is mapped as one 32-bit location that consists of two 16-bit registers. One register is for write operations and transfers data to the transmit FIFO. The other is for read operations and takes data from the receive FIFO. A write cycle, or burst write, loads successive half-words into the transmit FIFO. The write data occupies the lower 2 bytes of the 32-bit word. A read cycle, or burst read, similarly transfers data from the receive FIFO. The FIFOs are independent buffers that allow full duplex operation.

•The SSPC Status Register (SSSR) indicates the state of the FIFO buffers, whether the programmable threshold has been passed, and whether a transmit or receive FIFO service request is active. It also shows how many entries are occupied in the FIFO. Flag bits are set when the SSPC is actively transmitting or receiving data, when the transmit FIFO is not full, and when the receive FIFO is not empty. An error bit signals an overrun of the receive FIFO.

When the registers are programmed, reserved bits must be written as zeros and are read as undefined.

8.7.1SSP Control Register 0 (SSCR0)

SSCR0, shown in Table 8-2, contains five bit fields that control SSP data size, frame format, external clock selection, clock divisor, and SSP enable. The SSE bit is reset to a zero state to ensure the SSP is disabled. The reset states for the other control bits are shown in the table, but each reset state must be set to the desired value before the SSPC is enabled.

8-8 Intel® PXA255 Processor Developer’s Manual