Memory Controller

Figure 6-35. SMROM Boot Time Configurations and Register Defaults

BOOT_SEL[2:0] = 110

16

SMROM

16-bit

 

 

 

(64 Mbit)

 

 

 

32

 

 

(nWORD = 0)

 

 

 

 

 

 

16

SMROM

 

16-bit

 

 

 

 

 

 

(64 Mbit)

 

 

 

 

 

 

(nWORD = 0)

 

 

 

 

MSC0

7FF0 7FF0

 

 

RBW0 = 0

 

 

 

 

 

SXCNFG

0004 4931

 

 

SXEN0 = 1h, SXCL0 = 4h (CL = 5),

SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits),

SXCA0 = 2h (9-bits), SXTP0 = 0h, SXLATCH=1h

MDREFR

03CA 7FFF

 

 

 

 

 

E0PIN = 1, K0RUN = 1

 

 

 

 

 

 

 

BOOT_SEL[2:0] = 100

SXMRS

0232 0232

 

 

 

BOOT_SEL[2:0] = 101

SXMRS

0232 0232

 

 

 

 

 

 

BOOT_SEL[2:0] = 110

SXMRS

0232 0232

 

 

 

BOOT_SEL[2:0] = 111

SXMRS

0232 0232

 

 

 

 

MRS value must be 0061h.

The number of banks in the device defaults to zero.

BOOT_SEL[2:0] = 111

16

SMROM

 

16-bit

 

(32 Mbit)

 

(nWORD = 0)

MSC0

7FF0 7FF8

 

 

RBW0 = 1

 

 

 

 

 

SXCNFG

0004 4531

 

 

SXEN0 = 1h, SXCL0 = 4h (CL = 5),

SXRL0 = 1h (RL = 2), SXRA0 = 1h (13-bits),

SXCA0 = 1h (8-bits), SXTP0 = 0h, SXLATCH=1h

MDREFR

03CA 7FFF

 

 

E0PIN = 1, K0RUN = 1

MRS value must be 0061h.

The number of banks in the device defaults to zero.

6.10.3Memory Interface Reset and Initialization

On reset, the SDRAM Interface is disabled. Reset values for the Boot ROM are determined by BOOT_SEL. The memory pins and controller are in the state shown in Table 6-42.

6-78

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Memory Interface Reset and Initialization, Smrom, Mdrefr 03CA 7FFF