Clocks and Power Manager

3.5.1Power Manager Control Register (PMCR)

The PMCR is used to select the manner in which Sleep Mode is entered when the nVDD_FAULT or the nBATT_FAULT pin is asserted low. When the IDAE bit is set, an Imprecise Data Abort indication is sent to the CPU. The CPU then performs an abort routine. Software must ensure that the abort routine sets the Sleep Mode configuration in the PWRMODE register (see Section 3.7.2, “Power Mode Register (PWRMODE)”). The IDAE bit is cleared in any Reset and when Sleep Mode exits. Software may also clear the IDAE bit when necessary. The PMCR must be protected through Memory Management Unit (MMU) permissions.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-7. PMCR Bit Definitions

 

0x40F0_0000

 

PMCR

 

 

Clocks and Power Manager

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31 30 29 28 27 26 25

24 23 22 21 20 19 18

17 16 15 14 13

12

11 10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

[31:1]

 

 

 

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read undefined and must always be written with zeroes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Imprecise Data Abort Enable.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 – Allow immediate entry to sleep mode when nVDD_FAULT or nBATT_FAULT is

 

 

 

0

 

 

IDAE

 

 

asserted.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 – Force imprecise data abort signal to CPU to allow software to enter sleep mode

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

when nVDD_FAULT or nBATT_FAULT is asserted. Recommended mode.

 

 

 

 

 

 

 

 

 

 

 

Cleared on hardware, watchdog, and GPIO reset, or when sleep mode exits.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IDAE

0

Intel® PXA255 Processor Developer’s Manual

3-23

Page 85
Image 85
Intel PXA255 manual Power Manager Control Register Pmcr, Pmcr Bit Definitions, Idae