Intel PXA255 manual Master Transactions Sheet 2, Idbr

I2C Bus Interface Unit

Table 9-5. Master Transactions (Sheet 2 of 2)

I2C Master	Mode of		Definition
Action	Operation
		•	I2C master operation data transmit mode.
		•	Occurs when the ISR[ITE] bit is set and the ICR[TB] bit is clear. If the
Write one data			IDBR Transmit Empty Interrupt is enabled, it is signalled to the
	Master-transmit		processor.
byte to the
	only	•	CPU writes one data byte to the IDBR, sets the appropriate START/
IDBR
			STOP bit combination, and sets the ICR[TB] bit to send the data.
			Eight bits are taken from the shift register and written to the serial
			bus. The eight bits are followed by a STOP, if requested.
Wait for		•	As a master-transmitter, the I2C unit generates the clock for the
Acknowledge	Master-transmit		acknowledge pulse. The I2C unit releases the SDA line to allow
from slave-	only		slave-receiver ACK transmission.
receiver		•	See Section 9.4.3.
		•	I2C master operation data receive mode.
		•	Eight bits are read from the serial bus, collected in the shift register
			then transferred to the IDBR after the ICR[ACKNAK] bit is read.
		•	The CPU reads the IDBR when the ISR[IRF] bit is set and the
			ICR[TB] bit is clear. If IDBR Receive Full Interrupt is enabled, it is
			signalled to the CPU.
		•	When the IDBR is read, if the ISR[ACKNAK] is clear (indicating
Read one byte	Master-receive		ACK), the processor writes the ICR[ACKNAK] bit and set the
of I2C Data			ICR[TB] bit to initiate the next byte read.
from the IDBR	only	•	If the ISR[ACKNAK] bit is set (indicating NAK), ICR[TB] bit is clear,
			ICR[STOP] bit is set, and ISR[UB] bit is set, then the last data byte
			has been read into the IDBR and the I2C unit is sending the STOP.
		•	If the ISR[ACKNAK] bit is set (indicating NAK), ICR[TB] bit is clear,
			but the ICR[STOP] bit is clear, then the CPU has two options: 1. set
			the ICR[START] bit, write a new target address to the IDBR, and set
			the ICR[TB] bit which will send a repeated start condition or 2. set
			the ICR[MA] bit and leave the ICR[TB] bit clear which will send a
			STOP only.
		•	As a master-receiver, the I2C unit will generate the clock for the
Transmit			acknowledge pulse. The I2C unit is also responsible for driving the
	Master-receive		SDA line during the ACK cycle.
Acknowledge
to slave-	only	•	If the next data byte is to be the last transaction, the CPU will set the
transmitter			ICR[ACKNAK] bit for NAK generation.
		•	See Section 9.4.3.
		•	If data chaining is desired, a repeated START condition is used
Generate a			instead of a STOP condition.
		•	This occurs after the last data byte of a transaction has been written
Repeated	Master-transmit
START to			to the bus.
	Master-receive
chain I2C		•	The CPU will write the next target slave address and the R/nW bit to
transactions			the IDBR, set the ICR[START] bit, and set the ICR[TB] bit.
		•	See Section 9.3.3.
Generate a	Master-transmit	•	Generated after the CPU writes the last data byte on the bus.
		•	CPU generates a STOP condition by setting the ICR[STOP] bit.
STOP	Master-receive
		•	See Section 9.3.3.

When the CPU needs to read data, the I2C unit transitions from slave-receive mode to master- transmit mode to transmit the start address, R/nW bit, and the ACK pulse. After it sends the ACK pulse, the I2C unit transitions to master-receive mode and waits to receive the read data from the slave device (see Figure 9-8).Multiple transactions can take place during an I2C operation. For example, transitioning from master-receive to master-transmit through a repeated start.

Intel® PXA255 Processor Developer’s Manual 9-13