Network SSP Serial Port

Figure 16-16. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=0 (master to frame)

SSPSCLK

 

 

 

 

(when SCMODE = 0)

 

 

 

 

SSPSCLK

 

 

 

 

(when SCMODE = 1)

 

 

 

 

SSPSCLK

 

 

 

 

(when SCMODE = 2)

 

 

 

 

SSPSCLK

 

 

 

 

(when SCMODE = 3)

 

 

 

 

SSPTXD

 

MSB

LSB

 

T1

T2

 

T3

T4

SSPRXD

Undefined

MSB

LSB

Undefined

SSPSFRM

(when SFRMP = 1)

T5T6

SSPSFRM

(when SFRMP = 0)

A9979-01

SSCR1[TTELP] can only be set to 1 in PSP mode if the SSP is a slave to frame. If SSCR1[TTE] is 1 and SSCR1[TTELP] is 1 and the SSP is a slave to frame, SSPTXD is driven at the same clock edge that the MSB is driven. SSPTXD is Hi-Z two clock edges after the clock edge that starts the LSB. This occurs even if the SSP is a master of clock and this clock edge does not appear on the SSPSCLK. If the SSP is a slave of clock, then the device driving SSPSCLK must provide another clock edge. Figure 16-17shows the pin timing for this mode.

Figure 16-17. PSP mode with SSCR1[TTE]=1 and SSCR1[TTELP]=1 (must be slave to frame)

SSPSCLK

 

 

 

 

(when SCMODE = 0)

 

 

 

 

SSPSCLK

 

 

 

 

(when SCMODE = 1)

 

 

 

 

SSPSCLK

 

 

 

 

(when SCMODE = 2)

 

 

 

 

SSPSCLK

 

 

 

 

(when SCMODE = 3)

 

 

 

 

SSPTXD

 

MSB

LSB

 

T1

T2

 

T3

T4

SSPRXD

Undefined

MSB

LSB

Undefined

SSPSFRM

(when SFRMP = 1)

T5T6

SSPSFRM

(when SFRMP = 0)

A9980-01

16-16

Intel® PXA255 Processor Developer’s Manual

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Intel manual Intel PXA255 Processor Developer’s Manual