Intel PXA255 manual Receive Overflow ROF, UDCCS4/9/14 Bit Definitions

USB Device Controller

Table 12-18. UDCCS4/9/14 Bit Definitions

0x 4060_0020	UDCCS4
0x 4060_0034	UDCCS9	USB Device Controller
0x4060_0048	UDCCS14

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

reserved

Reset x x x x x x x x x x x x x x x x x x x x x x x x

7	6	5	4	3	2	1	0
RSP	RNE	reserved		DME	ROF	RPC	RFS
0	0	0	0	0	0	0	0

Bits	Name	Description
31:8	—	reserved
7	RSP	Receive short packet (read-only)
		1 = Short packet received and ready for reading.
		Receive FIFO not empty (read-only).
6	RNE	0 = Receive FIFO empty.
		1 = Receive FIFO not empty.
5:4	—	reserved
		DMA Enable(read/write)
3	DME	0 = Send receive interrupt after EOP receive
		1 = Send data received interrupt after EOP received and Receive FIFO has < 32 bytes of
		data
2	ROF	Receive overflow (read/write 1 to clear)
		1 = Isochronous data packets are being dropped from the host because the receiver is full.

Receive packet complete (read/write 1 to clear).

1	RPC	0 =	Error/status bits invalid.
		1 = Receive packet has been received and error/status bits are valid.
0	RFS	Receive FIFO service (read-only).
		0 = Receive FIFO has less than 1 data packet.
		1 =	Receive FIFO has 1 or more data packets.

12.6.7.1Receive FIFO Service (RFS)

The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the packet has been error checked by the UDC. A complete packet may be 256 bytes, a short packet, or a zero packet. UDCCSx[RFS] is not cleared until all data is read from both buffers.

12.6.7.2Receive Packet Complete (RPC)

The receive packet complete bit gets set by the UDC when an OUT packet is received. When this bit is set, the IRx bit in the appropriate UDC status/interrupt register is set if receive interrupts are enabled. This bit can be used to validate the other status/error bits in the endpoint(x) control/status register. The UDCCSx[RPC] bit is cleared by writing a 1 to it.

12.6.7.3Receive Overflow (ROF)

The receive overflow bit generates an interrupt on IRx in the appropriate UDC status/interrupt register to alert the software that Isochronous data packets are being dropped because neither FIFO buffer has room for them. This bit is cleared by writing a 1 to it.

Intel® PXA255 Processor Developer’s Manual 12-33