Intel PXA255 manual Trailing Bytes in the Receive Fifo, Data Formats

Network SSP Serial Port

The FIFOs can also be accessed by DMA bursts (in multiples of one, two or four bytes) depending upon the EDSS value. When SSCR0[EDSS] is set, DMA bursts must be in multiples of four bytes (the DMA must have the SSP configured as a 32-bit peripheral).When SSCR0[EDSS] is cleared, DMA bursts must be in multiples of one or two bytes (the DMA’s DCMD[WIDTH] register must be at least the SSP data size programmed into the SSCR0[EDSS] and SSCR0[DSS]. If the DMA DCMD[WIDTH] field is configured for 1 byte width, the DMA burst size must be 8 or 16.

For writes, the SSP takes the data from the transmit FIFO, serializes it, and sends it over the serial wire (SSPTXD) to the external device. Receive data from the external device (on SSPRXD) is converted to parallel words and stored in the receive FIFO.

When exceeded, a programmable trigger threshold generates an interrupt or DMA service request that, if SSCR1[TIE] or SSCR1[TSRE] are enabled, signal the CPU or DMA, respectively, to refill the transmit FIFO. Similarly, a programmable trigger threshold generates an interrupt or DMA service request that, if SSCR1[RIE] or SSCR1[RSRE] are enabled, signal the CPU or DMA, respectively, to empty the receive FIFO.

The receive and transmit FIFOs are differentiated by whether the access is a read or a write transfer. Reads automatically target the receive FIFO, while writes write data to the transmit FIFO. From a memory-map perspective, both reads and writes are at the same address. The FIFOs are 16 samples deep by one word wide.

16.4.2Trailing Bytes in the Receive FIFO

When the number of samples in the receive FIFO is less than the trigger threshold and no additional data is received, the remaining bytes are called trailing bytes. Trailing bytes must be handled by the processor. Trailing bytes are identified via a time-out mechanism and the existence of data within the receive FIFO.

16.4.2.1Time-out

A time-out condition exists when the receive FIFO is idle for the period of time defined by the Time-Out Register (SSTO). When a time-out occurs, the receiver time-out interrupt (SSSR[TINT]) is set. If the time-out interrupt is enabled (SSCR1[TINTE] set) a time-out interrupt occurs to signal the processor that a time-out condition has occurred. The time-out timer is reset after receiving a new sample or after the processor reads the receive FIFO. Once SSSR[TINT] is set it must be cleared by writing a one to it. If the time-out interrupt is enabled, clearing SSCR1[TINTE] also causes the time-out interrupt to be de-asserted.

16.4.2.2Removing Trailing Bytes

In this case, no receive DMA service request is generated. To read out the trailing bytes, have the software wait for the time-out interrupt and then read all remaining entries as indicated by SSSR[RFL] and SSSR[RNE].

Note: The time-out interrupt must be enabled by setting SSCR1[TINTE].

16.4.3Data Formats

Four pins transfer data between the PXA255 processor and external CODECs or modems. Although four serial-data formats exist, each has the same basic structure and in all cases the pins are used as follows:

Intel® PXA255 Processor Developer’s Manual 16-3