UARTs

Table 10-13. LSR Bit Definitions (Sheet 3 of 3)

Base+0x14

Line Status Register

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

reserved

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

UART

7 6 5 4 3 2 1 0

FIFOE TEMT TDRQ BI FE PE OE DR

0 1 1 0 0 0 0 0

Bits

Name

Description

 

 

 

 

 

Parity Error: Indicates that the received data character does not have the correct even or

 

 

odd parity, as selected by the even parity select bit. PE is set upon detection of a parity

2

PE

error and is cleared when the processor reads the LSR. In FIFO mode, PE shows a parity

error for the character at the front of the FIFO, not the most recently received character.

 

 

 

 

0 – No Parity error

 

 

1 – Parity error has occurred

 

 

 

 

 

Overrun Error: In non-FIFO mode, indicates that data in the Receive Buffer Register was

 

 

not read by the processor before the next character was received. The new character is

 

 

lost. In FIFO mode, OE indicates that all 64 bytes of the FIFO are full and the most recently

1

OE

received byte has been discarded. The OE indicator is set upon detection of an overrun

 

 

condition and cleared when the processor reads the LSR.

 

 

0 – No data has been lost

 

 

1 – Received data has been lost

 

 

 

 

 

Data Ready: Set when a complete incoming character has been received and transferred

 

 

into the Receive Buffer Register or the FIFO. In non-FIFO mode, DR is cleared when the

0

DR

receive buffer is read. In FIFO mode, DR is cleared if the FIFO is empty (last character has

been read from RBR) or the FIFO is reset with FCR[RESETRF].

 

 

 

 

0 – No data has been received

 

 

1 – Data is available in RBR or the FIFO

 

 

 

Intel® PXA255 Processor Developer’s Manual

10-17

Page 375
Image 375
Intel PXA255 manual LSR Bit Definitions Sheet 3