Contents

9-3

START and STOP Conditions

9-6

9-4

Data Format of First Byte in Master Transaction

9-8

9-5

Acknowledge on the I2C Bus

9-9

9-6

Clock Synchronization During the Arbitration Procedure

9-10

9-7

Arbitration Procedure of Two Masters

9-11

9-8

Master-Receiver Read from Slave-Transmitter

9-14

9-9

Master-Receiver Read from Slave-Transmitter / Repeated Start / Master-

 

 

Transmitter Write to Slave-Receiver

9-14

9-10

A Complete Data Transfer

9-14

9-11

Master-Transmitter Write to Slave-Receiver

9-16

9-12

Master-Receiver Read to Slave-Transmitter

9-16

9-13

Master-Receiver Read to Slave-Transmitter, Repeated START, Master-

 

 

Transmitter Write to Slave-Receiver

9-16

9-14

General Call Address

9-17

10-1

Example UART Data Frame

10-4

10-2

Example NRZ Bit Encoding – (0b0100 1011

10-5

10-3

IR Transmit and Receive Example

10-25

10-4

XMODE Example

10-25

11-1

4PPM Modulation Encodings

11-2

11-2

4PPM Modulation Example

11-2

11-3

Frame Format for IrDA Transmission (4.0 Mbps)

11-3

12-1

NRZI Bit Encoding Example

12-4

12-2

Self-Powered Device

12-11

13-1

Data Transfer Through the AC-link

13-3

13-2

AC’97 Standard Bidirectional Audio Frame

13-4

13-3

AC-link Audio Output Frame

13-5

13-4

Start of Audio Output Frame

13-5

13-5

AC’97 Input Frame

13-9

13-6

Start of an Audio Input Frame

13-9

13-7

AC-link Powerdown Timing

13-12

13-8

SDATA_IN Wake Up Signaling

13-13

13-9

PCM Transmit and Receive Operation

13-27

13-10

Mic-inReceive-Only Operation

13-29

13-11

Modem Transmit and Receive Operation

13-32

14-1

I2S Data Formats (16 bits)

14-7

14-2

MSB-Justified Data Formats (16 bits

14-7

14-3

Transmit and Receive FIFO Accesses Through the SADR

14-15

15-1

MMC System Interaction

15-1

15-2

MMC Mode Operation Without Data Token

15-3

15-3

MMC Mode Operation With Data Token

15-3

15-4

SPI Mode Operation Without Data Token

15-4

15-5

SPI Mode Read Operation

15-4

15-6

SPI Mode Write Operation

15-4

16-1

Texas Instruments Synchronous Serial Frame* Protocol (multiple transfers)

16-5

16-2

Texas Instruments Synchronous Serial Frame* Protocol (single transfers)

16-6

16-3

Motorola SPI* Frame Protocol (multiple transfers)

16-7

16-4

Motorola SPI* Frame Protocol (single transfers)

16-7

16-5

Motorola SPI* Frame Protocols for SPO and SPH Programming (multiple transfers)

16-8

16-6

Motorola SPI* Frame Protocols for SPO and SPH Programming (single transfers)

16-9

16-7

National Semiconductor Microwire* Frame Protocol (multiple transfers)

16-10

Intel® PXA255 Processor Developer’s Manual

xv

Page 15
Image 15
Intel PXA255 manual 10-25