Clocks and Power Manager

3.5.4Power Manager Rising-Edge Detect Enable Register (PRER)

The PRER, shown in Table 3-10, determines whether the GPIO pin enabled with the PWER register causes a wake up from sleep mode on that GPIO pin’s rising edge. When PWER[IDAE] is zero and a fault condition is detected on the nVDD_FAULT or nBATT_FAULT pin, PRER is set to 0x0000_0003. This enables rising edges on GP[1:0] to act as wake up sources. When PWER[IDAE] is set, fault conditions on the nVDD_FAULT or nBATT_FAULT pins do not affect wake-up sources. PRER is also set to 0x0000_0003 in hardware, watchdog, and GPIO resets.

Software should enable wakeups only for those GPIO pins that are configured as inputs during sleep. Any GPIO pins that are configured as outputs during sleep, should have their associated wake enable bits set to logic zero in all three PMU wake enable registers (PWER, PRER, and PFER).

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-10. PRER Bit Definitions

 

 

 

 

0x40F0_0010

 

 

 

 

 

 

 

 

PRER

 

 

 

 

 

 

Clocks and Power Manager

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31 30 29 28 27

26

25 24 23

22 21 20

19

18 17 16 15

14 13 12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved

 

 

 

 

 

 

 

 

RE15

RE14

RE13

RE12

RE11

RE10

RE9

RE8

RE7

RE6

RE5

RE4

RE3

RE2

RE1

RE0

Reset

0

0

0

0

0

0

 

0

0

 

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[31:16]

 

 

 

 

 

Reserved.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read undefined and must always be written with zeroes.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sleep mode Rising-edge Wake up Enable

 

 

 

 

 

 

 

 

 

 

 

 

 

 

[15:0]

 

 

REx

 

 

0 – Wake up due to GPx rising-edge detect disabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 – Wake up due to GPx rising-edge detect enabled.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Set to 0x 0003 on hardware, watchdog, and GPIO resets.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

3-26

Intel® PXA255 Processor Developer’s Manual

Page 88
Image 88
Intel PXA255 manual Power Manager Rising-Edge Detect Enable Register Prer, Prer Bit Definitions, 0x40F00010