Intel PXA255 manual Transmit and Receive FIFOs

Fast Infrared Communication Port

A minimum of 16 preambles are transmitted for each frame. If data is not available after the sixteenth preamble, additional preambles are transmitted until a byte of valid data resides in the bottom of the transmit FIFO. The preambles are followed by the start flag and the data from the transmit FIFO. Groups of four chips (eight bits) are encoded and loaded in a serial shift register. The contents of the serial shift register are sent out on the transmit data pin, which is clocked by the 8-MHz baud clock. The preamble, start and stop flags, and CRC value are transmitted automatically.

When the transmit FIFO has 32 or more empty entries, an interrupt (if enabled) and DMA service request are sent. If new data does not arrive quickly enough to prevent the FIFO from becoming empty, the transmit logic attempts to transfer additional data from the empty FIFO. Software determines whether to interpret the data underrun (a lack of data) as a signal of normal frame completion or as an unexpected frame termination.

When software selects normal frame completion and an underrun occurs, the transmit logic transmits the CRC value that was calculated during data transmission, including the address and control bytes, followed by the stop flag that marks the end of the frame. The transmitter then continuously transmits preambles until data is available in the FIFO. When data is available, the transmitter starts to transmit the next frame.

When software selects unexpected frame termination and an underrun occurs, the transmit logic transmits an abort and interrupts the CPU. The transmitter continues to send the abort until data is available in the transmit FIFO. When data is available, the FICP transmits 16 preambles and a start flag and starts the new frame. The off-chip receiver can choose to ignore the abort and continue to receive data or signal the FICP to attempt to transmit the aborted frame again.

At the end of each transmitted frame, the FICP sends a pulse called the serial infrared interaction pulse (SIP). A SIP must be sent at least every 500 ms to ensure that low-speed devices (115.2 Kbps and slower) do not interfere with devices that transmit at higher speeds. The SIP simulates a start bit that causes low-speed devices to stay off the air for at least another 500 ms. The SIP pulse forces the transmit data pin high for 1.625 µs and low for 7.375 µs (the total SIP period is 9.0 µs). After the SIP period, the preamble is transmitted continuously to indicate to the off-chip receiver that the FICP’s transmitter is in the idle state. The preamble is transmitted until new data is available in the transmit FIFO or the FICP’s transmitter is disabled. At least one frame must be completed every 500 ms to ensure that an SIP pulse can keep low-speed devices from interrupting the transmission. Because most IrDA compatible devices produce an SIP after each frame transmitted, software only needs to ensure that a frame is either transmitted or received by the FICP every 500 ms. Frame length does not represent a significant portion of the 500 ms timeframe in which an SIP must be produced. At 4.0 Mbps, the longest frame allowed is 16,568 bits, which takes just over 4 ms to transmit. The FICP also issues an SIP when the transmitter is first enabled. This ensures that low-speed devices do not interfere as the FICP transmits its data.

If software disables the FICP’s transmitter during operation, data transmission stops immediately, the serial shifter and transmit FIFO are cleared, and the SIU takes control of the transmit data pin. The transmit data output’s polarity must be properly reprogrammed if the pin is used as a GPIO output.

11.2.10Transmit and Receive FIFOs

The transmit FIFO is 128 entries deep and 8 bits wide. The receive FIFO is 128 entries deep,

11 bits wide. The receive FIFO uses 3 bits of its entries as status bits. The transmit FIFO and the receive FIFO use two separate, dedicated DMA requests.

11-6 Intel® PXA255 Processor Developer’s Manual