Memory Controller

Figure 6-23. Asynchronous 32-Bit Flash Write Timing Diagram (2 Writes)

 

0ns

50ns

100ns

150ns

200ns

CLK_MEM

 

 

 

 

 

 

 

 

RRR*2+1

 

 

nCS[0]

 

 

 

 

 

 

tAS

 

 

tAS

 

MA[25:2]

command address

data address

 

MA[1:0]

 

'0'

 

'0'

 

 

tCES

 

tCEH

tCES

tCEH

 

tASW

 

tAH

tASW

tAH

 

 

RDF+1

 

RDF+1

 

nWE

 

 

 

 

 

nOE

 

 

 

 

 

RDnWR

 

 

 

 

 

 

 

tDSWH

tDH

tDSWH

tDH

 

 

 

 

MD[31:0]

 

CMD

 

DATA

 

DQM[3:0]

 

"00"

 

"00"

 

nADV(nSDCAS)

*A command and data write to Flash MSC0:RDF0 = 2, RRR0 = 2

tAS = Address Setup to nCS asserted = 1 clk_mem tAH = Address Hold from nWE deasserted = 2 clk_mem tASW = Address Setup to nWE asserted = 3 clk_mem tCES = nCS setup to nWE asserted = 2 clk_mems tCEH = nCS hold from nWE deasserted = 1 clk_mem

tDSWH = MD/DQM setup to nWE deasserted = RDF+2 clk_mems tDH = MD/DQM hold from nWE deasserted = 1 clk_mem

In Figure 6-23some of the parameters are defined as follows:

tAS = Address setup to nCS = 1 MEMCLK

tCES = nCS setup to nWE = 2 MEMCLKs

tASW = Address setup time to nWE asserted = 3 MEMCLKs

tDSWH = Write data, DQM setup to nWE deasserted = (RDF+2) MEMCLKs

tDH = Data, DQM hold after nWE deasserted = 1 MEMCLKs

tCEH = nCS held asserted after nWE deasserted = 1 MEMCLK

tAH = Address hold after nWE deasserted = 1 MEMCLKs

Intel® PXA255 Processor Developer’s Manual

6-59

Page 241
Image 241
Intel PXA255 manual Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes, CMD Data