System Architecture

Table 2-5. Processor Pin Types

Type

Function

 

 

IA

Analog Input

 

 

OA

Analog output

 

 

IAOA

Analog bidirectional

 

 

SUP

Supply pin (either VCC or VSS)

 

 

Table 2-6describes the PXA255 processor pins.

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 1 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

Memory Controller Pins

 

 

 

MA[25:0]

OCZ

Memory address bus. (output) Signals the address

Driven Low

Driven Low

requested for memory accesses.

 

 

 

 

 

 

 

 

 

MD[15:0]

ICOCZ

Memory data bus. (input/output) Lower 16 bits of the

Hi-Z

Driven Low

data bus.

 

 

 

 

 

 

 

 

 

MD[31:16]

ICOCZ

Memory data bus. (input/output) Used for 32-bit

Hi-Z

Driven Low

memories.

 

 

 

 

 

 

 

 

 

nOE

OCZ

Memory output enable. (output) Connect to the output

Driven High

Note [4]

enables of memory devices to control data bus drivers.

 

 

 

 

 

 

 

 

 

nWE

OCZ

Memory write enable. (output) Connect to the write

Driven High

Note [4]

enables of memory devices.

 

 

 

 

 

 

 

 

 

 

 

SDRAM CS for banks 3 through 0. (output) Connect to

 

 

nSDCS[3:0]

OCZ

the chip select (CS) pins for SDRAM. For the PXA255

Driven High

Note [5]

 

 

processor nSDCS0 can be Hi-Z, nSDCS1-3 cannot.

 

 

 

 

 

 

 

 

 

SDRAM DQM for data bytes 3 through 0. (output)

 

 

DQM[3:0]

OCZ

Connect to the data output mask enables (DQM) for

Driven Low

Driven Low

 

 

SDRAM.

 

 

 

 

 

 

 

nSDRAS

OCZ

SDRAM RAS. (output) Connect to the row address

Driven High

Driven High

strobe (RAS) pins for all banks of SDRAM.

 

 

 

 

 

 

 

 

 

nSDCAS

OCZ

SDRAM CAS. (output) Connect to the column address

Driven High

Driven High

strobe (CAS) pins for all banks of SDRAM.

 

 

 

 

 

 

 

 

 

 

 

Synchronous Static Memory clock enable. (output)

 

 

SDCKE[0]

OC

Connect to the CKE pins of SMROM. The memory

Driven Low

Driven Low

 

 

controller provides control register bits for deassertion.

 

 

 

 

 

 

 

 

 

SDRAM and/or Synchronous Static Memory clock

 

 

 

 

enable. (output) Connect to the clock enable pins of

 

 

SDCKE[1]

OC

SDRAM. It is deasserted during sleep. SDCKE[1] is

Driven Low

Driven Low

 

 

always deasserted upon reset. The memory controller

 

 

 

 

provides control register bits for deassertion.

 

 

 

 

 

 

 

 

 

Synchronous Static Memory clock. (output) Connect to

 

 

 

 

the clock (CLK) pins of SMROM. It is driven by either the

 

 

 

 

internal memory controller clock, or the internal memory

 

 

 

 

controller clock divided by 2. At reset, all clock pins are

 

 

 

 

free running at the divide by 2 clock speed and may be

 

 

SDCLK[0]

OC

turned off via free running control register bits in the

 

 

 

 

memory controller. The memory controller also provides

 

 

 

 

control register bits for clock division and deassertion of

 

 

 

 

each SDCLK pin. SDCLK[0] control register assertion bit

 

 

 

 

defaults to on if the boot-time static memory bank 0 is

 

 

 

 

configured for SMROM.

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

2-9

Page 39
Image 39
Intel manual Pin & Signal Descriptions for the PXA255 Processor Sheet 1