Intel PXA255 Dmac Channels, Signal Descriptions, DREQ10 and PREQ370 Signals, Dmac Signal List

DMA Controller

5.1.1DMAC Channels

The DMAC has 16 channels, each controlled by four 32-bit registers. Each channel can be configured to service any internal peripheral or one of the external peripherals for flow-through transfers. Each channel is serviced in increments of the peripheral device’s burst size and is delivered in the granularity appropriate to that device’s port width. The burst size and port width for each device is programmed in the channel registers and is based on the device’s FIFO depth and bandwidth needs. Due to performance issues, it is highly recommended that the user set the burst size equal to the FIFO DMA interrupt trigger level, also called the FIFO threshold level. When multiple channels are actively executing, the DMAC services each channel with a burst of data. After the data burst is sent, the DMAC may perform a context switch to another active channel. The DMAC performs context switches based on a channel’s activity, whether its target device is currently requesting service, and where that channel lies in the priority scheme.

Channel information must be maintained on a per-channel basis and is contained in the DMAC registers see in Table 5-13. The DMAC supports two methods of loading the DMAC register, No- Descriptor and Descriptor Fetch Modes. The fetch modes are discussed in further detail in Section 5.1.4.

Software must ensure cache coherency when it configures the DMA channels. The DMAC does not check the cache so target and source addresses must be configured as non-cacheable in the Memory Management Unit.

Each demand for data that a peripheral generates results in a read or write to memory data. A peripheral must not request a DMA transfer unless it is prepared to read or write the full data block (8, 16, or 32 bytes) and it is equipped to handle reads and writes less than a full data block. Reads and writes less than a full data block can occur at the end of a DMA transfer.

5.1.2Signal Descriptions

The DREQ[1:0], PREQ[37:0] and DMA_IRQ signals are controlled by the DMAC as indicated in Table 5-1.

Table 5-1. DMAC Signal List

Signal	Signal Type	To/From	Definition
	In/Out
DREQ[1:0]	Input	Pins	External companion chip request lines. DMA detects the
			positive edge of this signal as a request.
DMA_IRQ	Output	Interrupt	Active high signal indicating an interrupt.
		Controller
			Internal peripheral DMA request lines. On chip peripherals
		On-chip	send requests using the PREQ signals.
PREQ[37:0]	Input		The DMAC does not sample the PREQ signals until it
		peripherals
			completely finishes the data transfer from peripheral to the
			memory.

5.1.2.1DREQ[1:0] and PREQ[37:0] Signals

The external companion chip asserts the positive edge triggered DREQ[1:0] signals when a DMA transfer request is needed. The DREQ[1:0] signal must remain asserted for four MEMCLKs to allow the DMA to recognize the 0 to 1 transition. When the DREQ[1:0] signals are deasserted, they

5-2 Intel® PXA255 Processor Developer’s Manual