Intel PXA255 manual Contents

				Contents
	4.2	Interrupt Controller		4-20
		4.2.1	Interrupt Controller Operation	4-20
		4.2.2 Interrupt Controller Register Definitions		4-21
	4.3	Real-Time Clock (RTC)		4-28
		4.3.1	Real-Time Clock Operation	4-28
		4.3.2	RTC Register Definitions	4-29
		4.3.3	Trim Procedure	4-32
	4.4	Operating System (OS) Timer		4-34
		4.4.1	Watchdog Timer Operation	4-35
		4.4.2 OS Timer Register Definitions		4-35
	4.5	Pulse Width Modulator		4-38
		4.5.1 Pulse Width Modulator Operation		4-38
		4.5.2	Register Descriptions	4-40
		4.5.3 Pulse Width Modulator Output Wave Example		4-43
	4.6	System Integration Unit Register Summary		4-44
		4.6.1	GPIO Register Locations	4-44
		4.6.2 Interrupt Controller Register Locations		4-45
		4.6.3 Real-Time Clock Register Locations		4-45
		4.6.4 OS Timer Register Locations		4-45
		4.6.5 Pulse Width Modulator Register Locations		4-46
5	DMA Controller			5-1
	5.1	DMA Description		5-1
		5.1.1	DMAC Channels	5-2
		5.1.2	Signal Descriptions	5-2
		5.1.3	DMA Channel Priority Scheme	5-3
		5.1.4	DMA Descriptors	5-5
		5.1.5	Channel States	5-8
		5.1.6 Read and Write Order		5-9
		5.1.7	Byte Transfer Order	5-9
		5.1.8	Trailing Bytes	5-10
	5.2	Transferring Data		5-11
		5.2.1	Servicing Internal Peripherals	5-11
		5.2.2 Quick Reference for DMA Programming		5-13
		5.2.3 Servicing Companion Chips and External Peripherals		5-14
		5.2.4	Memory-to-Memory Moves	5-16
	5.3	DMAC Registers		5-17
		5.3.1	DMA Interrupt Register (DINT)	5-17
		5.3.2 DMA Channel Control/Status Register (DCSRx)		5-17
		5.3.3 DMA Request to Channel Map Registers (DRCMRx)		5-20
		5.3.4 DMA Descriptor Address Registers (DDADRx)		5-20
		5.3.5 DMA Source Address Registers		5-21
		5.3.6 DMA Target Address Registers (DTADRx)		5-22
		5.3.7 DMA Command Registers (DCMDx)		5-23
	5.4	Examples		5-26
	5.5	DMA Controller Register Summary		5-28
6	Memory Controller			6-1
	6.1	Overview		6-1
	6.2	Functional Description		6-2
Intel® PXA255 Processor Developer’s Manual				v