Intel PXA255 manual UDC Interrupt Control Register 0 UICR0, Transmit Underrun TUR

USB Device Controller

12.6.8.4Transmit Underrun (TUR)

The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When the UDC experiences an underrun, NAK handshakes are sent to the host. UDCCSx[TUR] does not generate an interrupt and is for status only. UDCCSx[TUR] is cleared by writing a 1 to it.

12.6.8.5Sent STALL (SST)

The sent stall bit is set by the UDC in response to FST successfully forcing a user induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation from the host PC when a STALL handshake is returned automatically. In either event, the core does not intervene and the UDC clears the STALL status when the host sends a CLEAR_FEATURE command. The endpoint operation continues normally and does not send another STALL condition, even if the UDCCSx[SST] bit is set. To allow the software to continue to send the STALL condition on the USB bus, the UDCCSx[FST] bit must be set again. The core writes a 1 to the sent stall bit to clear it.

12.6.8.6Force STALL (FST)

The core can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes continue to be sent until the core clears this bit by sending a Clear Feature command. The UDCCSx[SST] bit is set when the STALL state is actually entered, but this may be delayed if the UDC is active when the UDCCSx[FST] bit is set. The UDCCSx[FST] bit is automatically cleared when the UDCCSx[SST] bit is set. To ensure that no data is transmitted after the Clear Feature command is sent and the host resumes IN requests, software must clear the transmit FIFO by setting the UDCCSx[FTF] bit.

12.6.8.7Bit 6 Reserved

Bit 6 is reserved for future use.

12.6.8.8Transmit Short Packet (TSP)

Software uses the transmit short to indicate that the last byte of a data transfer has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized packet is ready to transmit. Software must not set this bit if a packet of 8 bytes is to be transmitted. When the data packet is successfully transmitted, the UDC clears this bit.

These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.

12.6.9UDC Interrupt Control Register 0 (UICR0)

UICR0, shown in Table 12-20, contains 8 control bits to enable/disable interrupt service requests from data endpoints 0 - 7. All of the UICR0 bits are reset to a 1 so interrupts are not generated on initial system reset.

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