System Architecture

2

2.1Overview

The PXA255 processor is an integrated system-on-a-chip microprocessor for high performance, low power portable handheld and handset devices. It incorporates the Intel XScale® microarchitecture with on-the-fly frequency scaling and sophisticated power management to provide industry leading MIPs/mW performance. The PXA255 processor is ARM* Architecture Version 5TE instruction set compliant (excluding floating point instructions) and follows the ARM* programmer’s model.

The processor’s memory interface supports a variety of memory types to allow design flexibility. Support for the connection of two companion chips permits a glueless interface to external devices. An integrated LCD display controller provides support for displays up to 640x480 pixels, and permits 1-, 2-, 4-, and 8-bit grayscale and 8- or 16-bit color pixels. A 256 entry/512 byte palette RAM provides flexibility in color mapping.

A set of serial devices and general system resources provide computational and connectivity capability for a variety of applications. Refer to Figure 2-1for an overview of the microprocessor system architecture.

Intel® PXA255 Processor Developer’s Manual

2-1

Page 31
Image 31
Intel PXA255 manual System Architecture, Overview