Manuals / Intel / Home Audio / Speaker System

Intel PXA255 DMA Target Address Registers DTADRx, DSADRx Bit Definitions, Source Address, Srcaddr

Models: PXA255

1 600

Download 600 pages 33.14 Kb

Page 172

DMA Controller

Table 5-10. DSADRx Bit Definitions

				0x4000_02x4								DMA Source Addr Register													DMA Controller
				0x4000_02x4										(DSADRx)											DMA Controller
														(DSADRx)

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

													SOURCE ADDRESS																		reserved
													SOURCE ADDRESS

Reset															Uninitialized

		Bits				Name													Description

									Source Address (read / write).
		31:3			SRCADDR				Address of the internal peripheral or address of a memory location.
									Address of a memory location for companion -chip transfer

									Source Address Bit 2
			2		SRCADDR				Reserved if DSADR.SrcAddr is an external memory location
									Not reserved if DSADR.SrcAddr is an internal peripheral (read / write).

		1:0				—			reserved

5.3.6DMA Target Address Registers (DTADRx)

To software, DTADRx (Table 5-11) is read only in the Descriptor Fetch Mode and is read/write in the No-Descriptor Fetch Mode.

These registers contain the target address for the current descriptor in a channel. The target address is the address of an internal peripheral or a memory location. On power up, the bits in this register are undefined. If the target address is the address of a companion chip or external peripheral, the target address must be aligned to an 8-byte boundary. This allows bits [2:0] of the address to be reserved. If the target address is the address for an internal peripheral, the address must be 32-bit aligned so that bits [1:0] are reserved. DTADRx must not contain the address of any other internal DMA, LCD, or MEMC register.

The DTADRx must not contain a flash address because writes to flash from the DMAC are not supported.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

5-22	Intel® PXA255 Processor Developer’s Manual

Image 172

Intel PXA255 manual DMA Target Address Registers DTADRx, DSADRx Bit Definitions, Source Address, Srcaddr

Contents

Intel PXA255 Processor Intel PXA255 Processor Developer’s Manual Contents Power Manager General Configuration Register Pcfr Contents Expansion Card Interface Timing Diagrams and Parameters DMA 10-1 11-1 12.6 14.3 15.5 Figures BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF = 10-25 Tables Clocks Manager Register Summary Sxcnfg 10-6 10-8 12-26 15-7 Revision History Date Revision DescriptionXxiv Intel XScale Microarchitecture Features System Integration FeaturesMemory Controller Clocks and Power ControllersUniversal Serial Bus USB Client DMA Controller Dmac LCD Controller6 AC97 Controller Inter-IC Sound I2S ControllerSynchronous Serial Protocol Controller Sspc Inter-Integrated Circuit I2C Bus Interface UnitGpio UARTsOS Timers Real-Time Clock RTCPulse-Width Modulator PWM Interrupt ControlIntroduction System Architecture OverviewIntel XScale Microarchitecture Implementation Options Coprocessor 7 Register 4 Psfs BitCoprocessor 14 Register 6 and 7- Clock and Power Management CPU Core Fault Register Bit DefinitionsCoprocessor 14 Registers 0-3 Performance Monitoring Coprocessor 15 Register 0 ID Register DefinitionCoprocessor 15 Register 1 P-Bit ID Bit DefinitionsPXA255 Processor ID Values ARM ID Jtag IDSemaphores I/O OrderingInterrupts Reset Unit Sleep Mode Gpio Reset Watchdog Reset Hard ResetUSB ICPInternal Registers Selecting Peripherals vs. General Purpose I/OPower on Reset and Boot Operation Power ManagementPin List Processor Pin TypesPin & Signal Descriptions for the PXA255 Processor Sheet 1 Pin Name Type Signal Descriptions Reset State Sleep StatePin & Signal Descriptions for the PXA255 Processor Sheet 2 Pin & Signal Descriptions for the PXA255 Processor Sheet 3 PsktselPin & Signal Descriptions for the PXA255 Processor Sheet 4 Pin & Signal Descriptions for the PXA255 Processor Sheet 5 Pin & Signal Descriptions for the PXA255 Processor Sheet 6 Pin & Signal Descriptions for the PXA255 Processor Sheet 7 Pin & Signal Descriptions for the PXA255 Processor Sheet 8 BootselRtcclk Icocz PwrenPin & Signal Descriptions for the PXA255 Processor Sheet 9 Pin Description Notes Sheet 1Memory Map Pin Description Notes Sheet 2Memory Map Part One From 0x80000000 to 0xFFFF Ffff Memory Map Part Two From 0x00000000 to 0x7FFF Ffff System Architecture Register Summary Unit Address Register Symbol Register DescriptionSystem Architecture Register Address Summary Sheet 1 System Architecture Register Address Summary Sheet 2 System Architecture Register Address Summary Sheet 3 System Architecture Register Address Summary Sheet 4 System Architecture Register Address Summary Sheet 5 UnitSystem Architecture Register Address Summary Sheet 6 System Architecture Register Address Summary Sheet 7 Unit AddressSystem Architecture Register Address Summary Sheet 8 System Architecture Register Address Summary Sheet 9 System Architecture Register Address Summary Sheet 10 System Architecture Register Address Summary Sheet 11 System Architecture Register Address Summary Sheet 12 Clocks and Power Manager Clock Manager IntroductionPower Manager Introduction Clock ManagerRetains Power in Sleep PWM SSPOST Ficp I2C MMC1 32.768 kHz Oscillator Core Phase Locked Loop2 3.6864 MHz Oscillator 4 95.85 MHz Peripheral Phase Locked Loop 5 147.46 MHz Peripheral Phase Locked LoopCore PLL Output Frequencies for 3.6864 MHz Crystal SdramHardware Reset Resets and Power ModesClock Gating Watchdog Reset Gpio Reset Completing a Watchdog ResetInvoking Gpio Reset Behavior During Gpio ResetRun Mode Turbo ModeCompleting Gpio Reset Entering Turbo ModeIdle Mode Behavior in Turbo ModeExiting Turbo Mode Entering Idle ModeBehavior in Idle Mode Exiting Idle ModeFrequency Change Sequence Preparing for a Frequency Change SequenceInvoking the Frequency Change Sequence Behavior During the Frequency Change Sequence8 33-MHz Idle Mode Completing the Frequency Change SequenceEntering 33-MHz Idle Mode Behavior in 33-MHz Idle ModeExiting 33-MHz Idle Mode Sleep ModeSleep Mode External Voltage Regulator Requirements Preparing for Sleep Mode Entering Sleep ModeClocks and Power Manager Behavior in Sleep Mode Exiting Sleep ModeClocks and Power Manager Power Mode Summary Power Mode Entry Sequence TablePower Mode Exit Sequence Table Sheet 1 IdlePower Mode Exit Sequence Table Sheet 2 Power Manager Registers Power Mode Supply Source Module Turbo RunPower Manager Control Register Pmcr Pmcr Bit DefinitionsPmcr IdaePower Manager General Configuration Register Pcfr Pcfr Bit DefinitionsPcfr OpdePower Manager Wake-Up Enable Register Pwer Pwer Bit DefinitionsWertc PwerPower Manager Rising-Edge Detect Enable Register Prer 10. Prer Bit Definitions0x40F00010 PrerPower Manager Falling-Edge Detect Enable Register Pfer 11. Pfer Bit Definitions0x40F00014 PferPower Manager Gpio Edge Detect Status Register Pedr 12. Pedr Bit Definitions0x40F00018 PedrPower Manager Sleep Status Register Pssr 13. Pssr Bit Definitions Sheet 1Pssr RDHPower Manager Scratch Pad Register Pspr 13. Pssr Bit Definitions Sheet 214. Pspr Bit Definitions CPU VFSPower Manager Fast Sleep Walk-up Configuration Register Pmfw 15. Pmfw Register Bitmap and Bit Definitions16. PGSR0 Bit Definitions 17. PGSR1 Bit DefinitionsPGSR0 SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0Reset Controller Status Register Rcsr Bit Reset 0x40F0002818. PGSR2 Bit Definitions PGSR2Core Clock Configuration Register Cccr Clocks Manager Registers19. Rcsr Bit Definitions Rcsr20. Cccr Bit Definitions 0x41300000Bit Reserved Multiplier =Clock Enable Register Cken 21. Cken Bit Definitions Sheet 1Description I2S Unit Clock Enable 21. Cken Bit Definitions Sheet 2CKEN8 CKEN5Oscillator Configuration Register Oscc Coprocessor 14 Clock and Power Management22. Oscc Bit Definitions 23. Coprocessor 14 Clock and Power Management Summary Core Clock Configuration Register Cclkcfg24. Cclkcfg Bit Definitions Power Mode Register Pwrmode Power-On-Reset ConsiderationsPower Supply Connectivity External Hardware ConsiderationsClocks and Power Manager Register Summary Driving the Crystal Pins from an External Clock SourcePower Manager Register Summary Clocks Manager Register Locations27. Power Manager Register Summary General-Purpose I/O Gpio OperationGeneral-Purpose I/O Block Diagram Gpio Alternate FunctionsGpio Alternate Functions Sheet 1 Gpio Alternate Functions Sheet 2 MMCCS0 ALTFN1OUT Gpio Alternate Functions Sheet 3Mbgnt ALTFN1OUT Gpio Alternate Functions Sheet 4 Gpio Register DefinitionsGpio Register Definitions Sheet 1 Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2 Gpio Register Definitions Sheet 2GPLR0 Bit Definitions GPLR0Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2 GPLR1 Bit DefinitionsGPLR2 Bit Definitions GPLR1GPDR1 Bit Definitions GPDR0 Bit DefinitionsGPDR2 Bit Definitions GPSR0 Bit Definitions 10. GPSR1 Bit DefinitionsGPSR0 PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS012. GPCR0 Bit Definitions 11. GPSR2 Bit Definitions13. GPCR1 Bit Definitions GPCR2 Bit Definitions GPCR216. GRER1 Bit Definitions 15. GRER0 Bit Definitions17. GRER2 Bit Definitions 19. GFER1 Bit Definitions 18. GFER0 Bit DefinitionsGFER2 Bit Definitions 21. GEDR0 Bit Definitions Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR222. GEDR1 Bit Definitions GEDR2 Bit Definitions GEDR224. GAFR0L Bit Definitions 25. GAFR0U Bit DefinitionsGAFR0L AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF026. GAFR1L Bit Definitions 27. GAFR1U Bit DefinitionsGAFR1L GAFR1U28. GAFR2L Bit Definitions 29. GAFR2U Bit DefinitionsGAFR2L GAFR2UInterrupt Controller Interrupt Controller OperationInterrupt Controller Block Diagram Interrupt Controller Register DefinitionsInterrupt Controller Mask Register Icmr Interrupt Controller Level Register Iclr30. Icmr Bit Definitions Icmr31. Iclr Bit Definitions Interrupt Controller Control Register Iccr32. Iccr Bit Definitions 33. Icip Bit Definitions 34. Icfp Bit DefinitionsInterrupt Controller Pending Register Icpr 35. Icpr Bit Definitions Sheet 1Icpr IS9 IS8Network SSP Service Request Interrupt Pending 35. Icpr Bit Definitions Sheet 2IS14 IS13 IS12 IS11 IS10 IS1635. Icpr Bit Definitions Sheet 3 36. List of First-Level Interrupts Sheet 1System Integration Unit Bit Position Source UnitReal-Time Clock Operation Real-Time Clock RTC36. List of First-Level Interrupts Sheet 2 RTC Register Definitions RTC Trim Register RttrRttr Bit Definitions RTC Alarm Register Rtar38. Rtar Bit Definitions RTC Counter Register Rcnr RTC Status Register Rtsr39. Rcnr Bit Definitions RcnrOscillator Frequency Calibration Trim Procedure40. Rtsr Bit Definitions Trim Example #1 Measured Value Has No Fractional Component Rttr Value CalculationsTrim Example #2 Measured Value Has a Fractional Component Operating System OS Timer Maximum Error Calculation Versus RTC AccuracyOS Timer Register Definitions Watchdog Timer OperationOS Timer Match Register 0-3 OSMRx OS Timer Interrupt Enable Register Oier 41. OSMRx Bit Definitions42. Oier Bit Definitions OSMR3, OSMR2, OSMR1OS Timer Watchdog Match Enable Register Ower OS Timer Count Register OscrOS Timer Status Register Ossr 43. Ower Bit Definitions0x40A00014 Bit Reset ? ? ? ? ? ? ? ? Bits Pulse Width ModulatorPulse Width Modulator Operation Ossr Bit DefinitionsPWMn Block Diagram 1.1 InterdependenciesReset Sequence Power Management RequirementsRegister Descriptions PWM Control Registers PWMCTRLnPWM Duty Cycle Registers PWMDUTYn 46. PWMCTRLn Bit Definitions0x40B00000 PrescalePWM Period Control Register PWMPERVALn 47. PWMDUTYn Bit DefinitionsPWMDUTY0, PWMDUTY1 Fdcycle Dcycle48. PWMPERVALn Bit Definitions Pulse Width Modulator Output Wave Example0x40B00008 Gpio Register Locations System Integration Unit Register Summary49. Gpio Register Addresses Sheet 1 Interrupt Controller Register Locations OS Timer Register LocationsReal-Time Clock Register Locations Pulse Width Modulator Register Locations 52. OS Timer Register Addresses Sheet 253. Pulse Width Modulator Register Addresses Dmac Block Diagram DMA DescriptionSignal Descriptions DREQ10 and PREQ370 SignalsDmac Signal List Signal Signal Type To/From Definition In/OutDmairq Signal DMA Channel Priority SchemeChannel Priority if all channels are running concurrently Channel PriorityNo-Descriptor Fetch Mode DMA DescriptorsPriority Schemes Examples DMA Channel PriorityDescriptor Fetch Mode No-Descriptor Fetch Mode Channel StateDMA Controller Channel States Servicing an InterruptRead and Write Order Byte Transfer OrderTrailing Bytes Little Endian TransfersTransferring Data Servicing Internal PeripheralsDcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg = Quick Reference for DMA Programming DMA Quick Reference for Internal Peripherals Sheet 1Dcmd DrcmrServicing Companion Chips and External Peripherals DMA Quick Reference for Internal Peripherals Sheet 2Unit Function Fifo Address Width Burst Size SourceDMA Controller Memory-to-Memory Moves Dmac Registers DMA Interrupt Register DintDMA Channel Control/Status Register DCSRx Dint Bit DefinitionsDCSRx Bit Definitions Sheet 1 RUNReqpend Stopstate Endintr Startintr BuserrintrReset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCSRx Bit Definitions Sheet 2DMA Request to Channel Map Registers DRCMRx DMA Descriptor Address Registers DDADRxDRCMRx Bit Definitions ChlnumDMA Source Address Registers DDADRx Bit DefinitionsDescriptor Address StopDMA Target Address Registers DTADRx 10. DSADRx Bit DefinitionsSource Address SrcaddrDMA Command Registers DCMDx 11. DTADRx Bit DefinitionsTarget Address Trgaddr12. DCMDx Bit Definitions Sheet 1 IncsrcaddrEndian Width Size12. DCMDx Bit Definitions Sheet 2 EndianWidth LengthExample 1. How to set up and start a channel ExamplesStruct longddadr longdsadr longdtadr shortlength shortdcmd DMA Controller Register Summary 13. DMA Controller Register Summary Sheet 113. DMA Controller Register Summary Sheet 2 13. DMA Controller Register Summary Sheet 3 13. DMA Controller Register Summary Sheet 4 13. DMA Controller Register Summary Sheet 5 Memory Controller Functional Description Sdram Interface OverviewStatic Memory Interface / Variable Latency I/O Interface Memory System Examples 3 16-Bit PC Card / Compact Flash InterfaceSdram Memory System Example Static Memory System Example Memory Accesses Device TransactionsBus Operation Burst Size Words BitsSynchronous Dram Memory Interface Reads and WritesAborts and Nonexistent Memory Sdram Mdcnfg Register MdcnfgMdcnfg Bit Definitions Sheet 1 Mdcnfg Bit Definitions Sheet 2 Mdcnfg Bit Definitions Sheet 3 DNB2DADDR2 DLATCH2Sdram Mode Register Set Configuration Register Mdmrs Mdmrs Bit Definitions Sheet 1Low-Power Sdram Mode Register Set Configuration Register Mdmrs Bit Definitions Sheet 2Sdram Mdrefr Register Mdrefr Mdmrslp Register Bit Definitions0X4800 MdmrslpMdrefr Bit Definitions Sheet 1 MdrefrAPD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PIN DRI0 1 0 0 1 * * 1 Mdrefr Bit Definitions Sheet 21 1 1 1 1 1 1 Mdrefr Bit Definitions Sheet 3 Fixed-Delay or Return-Clock Data LatchingAPD Sdram Memory Options Sdram Addressing ModesSample Sdram Memory Size Options Number Chips Partition Size‘0’ # Bits1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32 MA2410 Col Data2x13x10x16 ‘0’ # Bits External Address pins at Sdram RAS Time Not Valid illegal addressing combinationMA24 MA23 MA20BA0 A10MA24 BA1 BA0A11 A10 Memory Controller Sdram Command Overview A1212. Sdram Mode Register Opcode Table 11. Sdram Command EncodingSdram Waveforms Sdclk DataSDRAMreadsamebankdiffrow SDRAMwrite SDCLK1 SDCKE1Synchronous Static Memory Configuration Register Sxcnfg Synchronous Static Memory Interface13. Sxcnfg Bit Definitions Sheet 1 0x4800001CSxcnfg SXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2Sxcnfg Bit Definitions Sheet 2 SXLATCH2SXRL2 SXCL2 SXEN2 SXLATCH013. Sxcnfg Bit Definitions Sheet 3 Smrom Memory Options Sxcnfg Bit Definitions Sheet 4SXCL0 SXEN0Smrom Synchronous Static Memory Timing Diagrams 16. Sxmrs Bit DefinitionsSxmrs SXMRS2Non-SDRAM Timing Sxmem Operation Sdclk Sdcke17. Read Configuration Register Programming Values Memclk SDCLK0 MdrefrNon-SDRAM Timing Flash Read Timing Diagram 12shows the burst-of-eight read timing diagramAsynchronous Static Memory 4.2 K3 Synchronous StrataFlash ResetStatic Memory Interface Sram 19 -Bit Bus Write Access 20 -Bit Bus Write AccessData Size MA10 DQM30 Data Size MA0 DQM1022 -Bit Byte Address Bit MA0 for Reads Based on DQM10 21 -Bit Byte Address Bits MA10 for Reads Based on DQM3023. SA-1111 Register Bit Definitions Asynchronous Static Memory Control Registers MSCx 24. MSC0/1/2 Bit Definitions Sheet 1 MSC0MSC1 MSC2Bits Access Name RRR1/3/5 RDN1/3/5 Reset RDF1/3/524. MSC0/1/2 Bit Definitions Sheet 2 24. MSC0/1/2 Bit Definitions Sheet 3 SramROM Interface Timing Memory Clocks MSCxRTx DeviceNOE NWE NOEROM Timing Diagrams and Parameters ClkmemRDN+1 Sram Timing Diagrams and Parameters Sram Interface Overview20shows the timing for Sram writes Variable Latency I/O Vlio Interface Overview Variable Latency I/O Timing Diagrams and Parameters RDF+1+Waits RRR*2+1RDF+1+Waits Flash Memory Timing Diagrams and Parameters Flash Memory Interface23. Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes CMD DataExpansion Memory Timing Configuration Register 16-Bit PC Card/Compact Flash Interface26. MCMEM0/1 Bit Definitions MCMEM027. MCATT0/1 Bit Definitions 28. MCIO0/1 Bit DefinitionsMCATT0 MCATT129. Card Interface Command Assertion Code Table MCMEMxASST XASSTHOLD XASSTWAIT +Expansion Memory Configuration Register Mecr 30. Mecr Bit DefinitionMecr CIT NOS3 16-Bit PC Card Overview 26 -Bit PC Card Memory Map31. Common Memory Space Write Commands 32. Common Memory Space Read Commands33. Attribute Memory Space Write Commands 34. Attribute Memory Space Read Commands38 -Bit I/O Space Read Commands nIOIS16 = 37 -Bit I/O Space Write Commands nIOIS16 =External Logic for 16-Bit PC Card Implementation DIR Socket Expansion Card Interface Timing Diagrams and Parameters 29 -Bit PC Card Memory or I/O 16-Bit Half-word Access30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device Companion Chip Interface31. Alternate Bus Master Mode 32. Variable Latency IOAlternate Bus Master Mode NVDDFAULT/nBATTFAULT with Pmcridae Disabled Gpio ResetNVDDFAULT/nBATTFAULT with Pmcridae Enabled Options and Settings for Boot Memory Alternate BootingBoot Time Defaults Bootdef Read-Only Register Bootdef40. Bootdef Bitmap 41. Valid Boot Configurations Based on Processor TypeBootdef PKG Type Boot SELBoot-Time Configurations Sxcnfg34. Smrom Boot Time Configurations and Register Defaults Smrom Memory Interface Reset and InitializationMdrefr 03CA 7FFF 42. Memory Controller Pin Reset Values Hardware, Watchdog, or Sleep Reset OperationPin Name PXA255 Processor Reset Value Memory Controller Gpio Reset Procedure Physical Address Symbol Register NameMemory Controller Register Summary 43. Memory Controller Register Summary Sheet 143. Memory Controller Register Summary Sheet 2 LCD Controller Features LCD ControllerLCD Controller Block Diagram LCD Controller Operation Pin DescriptionsEnabling the Controller Pin DescriptionsResetting the Controller Detailed Module DescriptionsDisabling the Controller Input FIFOsLookup Palette Temporal Modulated Energy Distribution Tmed DitheringCompare Range for Tmed Output FIFOs LCD Controller Pin UsagePixel Data Pins LDDx 6 DMAPassive Display Timing Active Display TimingLCD External Palette and Frame Buffers External Palette BufferExternal Frame Buffer Palette Buffer FormatBits Per Pixel Data Memory Organization 10 Bits Per Pixel Data Memory Organization Passive Mode Functional Timing FrameBufferSize =12. Passive Mode Start-of-Frame Timing Vsync Hsync LbiasRegister Descriptions Lfclk Vsync Llclk Hsync LbiasLCD Controller Control Register 0 LCCR0 LCD Controller LDD LCD Controller Data Pin Utilization Sheet 1 Single Passive Screen Portion Pins LCD Controller Data Pin Utilization Sheet 2Reset X X X X X X X X X X X LCCR0 Bit Definitions Sheet 1LCCR0 0x44000000 Bit ReservedLCD Controller Control Register 1 LCCR1 LCCR0 Bit Definitions Sheet 2QDM DIS DPD PAS EFM IUM SFM LDM SDS CMS ENBLCD Controller LCD Controller Control Register 2 LCCR2 LCCR1 Bit DefinitionsBLW ELW HSW PPL BLWLCD Controller LCD Controller Control Register 3 LCCR3 LCCR2 Bit DefinitionsBFW EFW VSW LPP BFWLCD Controller LCD Controller Reset X X X X 0 0 0 LCCR3 Bit Definitions Sheet 10x4400000C Bit Reserved DPC BPPReset X X X LCD Controller DMAFrame Descriptors LCCR3 Bit Definitions Sheet 2LCD DMA Frame Descriptor Address Registers FDADRx LCD DMA Frame Source Address Registers FSADRxFDADRx Bit Definitions FDADR0FSADRx Bit Definitions LCD DMA Frame ID Registers FIDRxFIDRx Bit Definitions LCD DMA Command Registers LDCMDx 10. LDCMDx Bit Definitions LDCMD0LDCMD1 PALLCD DMA Frame Branch Registers FBRx 11. FBRx Bit DefinitionsBint BRA 0 0 0 0 X X 0 Bits Name DescriptionLCD Controller Status Register Lcsr LCD Controller 0x44000038 Bit Reset X X Lcsr Bit Definitions Sheet 1X X EOF IUU IUL ABC BER SOF LDDLCD Controller Interrupt ID Register Liidr 12. Lcsr Bit Definitions Sheet 213. Liicr Bit Definitions Sint BS EOF QD OU IUU IUL ABC BER SOF LDDTmed RGB Seed Register Trgbr 14. Trgbr Bit DefinitionsTBS TRSTmed Control Register TCR 15. TCR Bit Definitions LCD Controller Register Summary16. LCD Controller Register Summary Sheet 1 16. LCD Controller Register Summary Sheet 2 LCD Controller Signal Description External Interface to Synchronous Serial PeripheralsExternal Interface to Codec Name Direction DescriptionData Transfer Data FormatsSerial Data Formats for Transfer to/from Peripherals SSP Format Details SPI Format Details Sspsclk SspsfrmSspsclk Sspsfrm MSB LSBMicrowire Format Details Sspsclk Sspsfrm Ssptxd SsprxdNational Microwire* Frame Format Parallel Data Formats for Fifo StorageUsing Programmed I/O Data Transfers Using DMA Data TransfersFifo Operation and Data Transfers Baud-Rate GenerationSSP Serial Port Registers SSP Control Register 0 SSCR0Data Size Select DSS SSCR0 Bit DefinitionsSSP Control Register 0 SSCR0 SCRFrame Format FRF Synchronous Serial Port Enable SSEExternal Clock Select ECS Serial Clock Rate SCR SSP Control Register 1 SSCR1SSCR1 Bit Definitions Sheet 1 Receive Fifo Interrupt Enable RIE Transmit Fifo Interrupt Enable TIELoop Back Mode LBM SSCR1 Bit Definitions Sheet 2Serial Clock Polarity SPO Serial Clock Phase SPHSspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Microwire Transmit Data Size Mwds Transmit Fifo Interrupt/DMA Threshold TFTReceive Fifo Interrupt/DMA Threshold RFT Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm SsptxdTFT and RFT Values for DMA Servicing SSP Data Register SsdrSsdr Bit Definitions SSP Status Register Sssr Transmit Fifo Not Full Flag TNF Sssr Bit DefinitionsRFL TFL ROR RFS TFS BSY RNE TNF RFLTransmit Fifo Service Request Flag TFS Receive Fifo Service Request Flag RFSReceive Fifo Not Empty Flag RNE SSP Busy Flag BSYSSP Controller Register Summary Receive Fifo Level RFLSSP Controller Register Summary Address Abbreviation Full NameSynchronous Serial Port Controller I2C Signal Description Signal Name Input/Output DescriptionSDA SCLI2C Bus Definitions 2C Device DefinitionMode Description Operational Blocks2 I2C Bus Interface Modes Modes of OperationStart and Stop Bus States Start and Stop Bit DefinitionsStop Star ConditionNo Start or Stop Condition Start ConditionStop Condition ACK NAK StartACK ACK Stop NAKSerial Clock Line SCL Generation I2C Bus OperationData and Addressing Management 3 I2C Acknowledge Addressing a Slave DevicePolling ArbitrationSCL Arbitration SDA ArbitrationArbitration Procedure of Two Masters Master Operations 2C Master Mode Definition Action OperationMaster Transactions Sheet 1 Master Transactions Sheet 2 Slave Operations Master-Receiver Read from Slave-Transmitter2C Slave Action Mode Definition Operation Slave TransactionsACK Stop General Call AddressNAK Stop General Call Address Second Byte Definitions Least SecondSlave Mode Programming Examples Initialize UnitWrite n Bytes as a Slave Read n Bytes as a SlaveMaster Programming Examples Write 1 Byte as a MasterRead 1 Byte as a Master Write 2 Bytes and Repeated Start Read 1 Byte as a MasterRead 2 Bytes as a Master Send Stop Using the Abort Reset ConditionsGlitch Suppression Logic Register Definitions 1 I2C Bus Monitor Register Ibmr2 I2C Data Buffer Register Idbr Ibmr Bit DefinitionsIdbr Bit Definitions 3 I2C Control Register ICR10. ICR Bit Definitions Sheet 1 40301690 Bit Reset Disable interrupt10. ICR Bit Definitions Sheet 2 Beie Irfie Iteie GCD IUE4 I2C Status Register ISR Receive mode10. ICR Bit Definitions Sheet 3 11. ISR Bit Definitions Sheet 1 2C Status Register40301698 Bit BED SAD5 I2C Slave Address Register Isar 11. ISR Bit Definitions Sheet 212. Isar Bit Definitions BED SAD Gcad IRF ITE ALD SSD IBBI2C Bus Interface Unit Feature List UARTsBluetooth Uart Full Function UartStandard Uart Compatibility withSignal Descriptions Uart Signal Descriptions Sheet 1Name Type Description RXDUart Operational Description Uart Signal Descriptions Sheet 2LSB MSB Reset Internal Register DescriptionsRegister Accessed Receive Buffer Register RBRUart Register Addresses as Offsets of a Base RBR Bit DefinitionsDivisor Latch Registers DLL and DLH Transmit Holding Register THRTHR Bit Definitions DLL Bit Definitions Interrupt Enable Register IERDLH Bit Definitions Interrupt Identification Register IIR IER Bit DefinitionsInterrupt Conditions IIR Bit Definitions Sheet 1Priority Level Interrupt origin FIFOES10Interrupt ID Bits Interrupt SET/RESET Function FcrresetrfIIR Bit Definitions Sheet 2 10. Interrupt Identification Register Decode Sheet 1Fifo Control Register FCR 10. Interrupt Identification Register Decode Sheet 211. FCR Bit Definitions Sheet 1 ITLLine Control Register LCR 11. FCR Bit Definitions Sheet 2Base+0x0C 12. LCR Bit DefinitionsUart Dlab Stkyp EPS PEN STB WLS1 WLS0 Line Status Register LSR 13. LSR Bit Definitions Sheet 1Fifoe Temt13. LSR Bit Definitions Sheet 2 Tdrq13. LSR Bit Definitions Sheet 3 Modem Control Register MCR 14. MCR Bit Definitions Sheet 1Uart Loop OUT2 OUT1 RTS DTR14. MCR Bit Definitions Sheet 2 Modem Status Register MSRBase+0x10 Modem Control Register 15. MSR Bit Definitions Fifo Interrupt Mode Operation Character Timeout Indication InterruptScratchpad Register SPR Receive InterruptDMA Requests Fifo Polled Mode OperationTransmit Interrupt Trailing Bytes in the Receive Fifo Slow Infrared Asynchronous InterfaceInfrared Selection Register ISR Operation 17. ISR Bit DefinitionsIR Transmit and Receive Example Uart Register Summary 18. Ffuart Register Summary19. Btuart Register Summary Sheet 1 Dlab Bit Name Description19. Btuart Register Summary Sheet 2 20. Stuart Register SummaryUart Register Differences 21. Flow Control Registers in Btuart and StuartBtmcr BtmsrFicp Signal Description Ficp Operation11.2.1 4PPM Modulation PPM Modulation EncodingsFrame Format Address FieldControl Field Data FieldBaud Rate Generation CRC FieldReceive Operation Transmit Operation Transmit and Receive FIFOs Trailing or Error Bytes in the Receive Fifo Ficp Register DefinitionsFicp Control Register 0 ICCR0 ICCR0 Bit Definitions Sheet 1ICCR0 Bit Definitions Sheet 2 TXETUS LBMFicp Control Register 1 ICCR1 ICCR1 Bit DefinitionsFicp Control Register 2 ICCR2 ICCR2 Bit DefinitionsFicp Data Register Icdr Icrd Bit DefinitionsFicp Status Register 0 ICSR0 ICSR0 Bit Definitions Sheet 1FRE RFSTUR ICSR0 Bit Definitions Sheet 2EIF Ficp Status Register 1 ICSR1 ICSR1 Bit DefinitionsFicp Register Summary Ficp Register SummaryUSB Device Controller USB OverviewDevice Configuration Endpoint ConfigurationUSB Protocol IN/OUTSignalling Levels Bit EncodingUSB States Bus State UDC+/UDC- Pin LevelsField Formats Nrzi Bit Encoding ExampleIN, OUT, and Setup Token Packet Format Packet FormatsToken Packet Type Start of Frame Packet TypeTransaction Formats Data Packet TypeHandshake Packet Type Bulk Transaction TypeIsochronous Transaction Type Control Transaction TypeBulk Transaction Formats Isochronous Transaction FormatsInterrupt Transaction Type UDC Device Requests10. Interrupt Transaction Formats 11. Host Device Request Summary ConfigurationRequest Name Self-Powered Device UDC Hardware ConnectionWhen GPIOn and GPIOx are Different Pins When GPIOn and GPIOx are the Same PinUDC Operation Bus-Powered DevicesCase 1 EP0 Control Read Case 2 EP0 Control Read with a Premature Status Stage 12-14 Intel PXA255 Processor Developer’s Manual Software Enables the DMA Case 4 EP0 No Data CommandCase 5 EP1 Data Transmit BULK-IN Software Enables the EP1 Interrupt Case 6 EP2 Data Receive BULK-OUTCase 7 EP3 Data Transmit ISOCHRONOUS-IN Software Enables DMASoftware Allows the Megacell to Handle the Transaction Software Enables the SOF Interrupt Software Enables the EP3 InterruptCase 8 EP4 Data Receive ISOCHRONOUS-OUT Intel PXA255 Processor Developer’s Manual 12-19 Case 10 Reset Interrupt Case 9 EP5 Data Transmit INTERRUPT-INCase 11 Suspend Interrupt UDC Register DefinitionsCase 12 Resume Interrupt UDC Control Register Udccr UDC Enable UDE12. Udccr Bit Definitions Reset Interrupt Request Rstir Reset Interrupt Mask REMUDC Active UDA UDC Resume RSMACK Control Mode ACK Response EnableUDC Control Function Register Udccfr 13. UDC Control Function RegisterUDC Endpoint 0 Control/Status Register UDCCS0 OUT Packet Ready OPRPacket Ready IPR 14. UDCCS0 Bit DefinitionsDevice Remote Wakeup Feature Drwf Flush Tx Fifo FTFSent Stall SST Force Stall FSTSetup Active SA Transmit Fifo Service TFSUDC Endpoint x Control/Status Register UDCCS1/6/11 15. UDCCS1/6/11 Bit DefinitionsTransmit Underrun TUR Transmit Packet Complete TPCBit 6 Reserved Transmit Short Packet TSP UDC Endpoint x Control/Status Register UDCCS2/7/1216. UDCCS2/7/12 Bit Definitions Receive Fifo Service RFS DMA Enable DMEReceive Packet Complete RPC Bit 2 ReservedReceive Short Packet RSP UDC Endpoint x Control/Status Register UDCCS3/8/1317. UDCCS3/8/13 Bit Definitions UDC Endpoint x Control/Status Register UDCCS4/9/14 Bits 64 ReservedReceive Overflow ROF 18. UDCCS4/9/14 Bit DefinitionsBits 54 Reserved UDC Endpoint x Control/Status Register UDCCS5/10/1519. UDCCS5/10/15 Bit Definitions Sheet 1 19. UDCCS5/10/15 Bit Definitions Sheet 2 UDC Interrupt Control Register 0 UICR0 Interrupt Mask Endpoint x IMx, Where x is 0 through 20. UICR0 Bit DefinitionsUICR0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0Interrupt Mask Endpoint x IMx, where x is 8 through UDC Interrupt Control Register 1 UICR121. UICR1 Bit Definitions UICR1UDC Status/Interrupt Register 0 USIR0 Endpoint 0 Interrupt Request IR0Endpoint 1 Interrupt Request IR1 22. USIR0 Bit DefinitionsEndpoint 2 Interrupt Request IR2 Endpoint 3 Interrupt Request IR3Endpoint 4 Interrupt Request IR4 Endpoint 5 Interrupt Request IR5UDC Status/Interrupt Register 1 USIR1 Endpoint 8 Interrupt Request IR8Endpoint 9 Interrupt Request IR9 Endpoint 10 Interrupt Request IR10UDC Frame Number High Register Ufnhr Isochronous Packet Error Endpoint 4 IPE4 Isochronous Packet Error Endpoint 9 IPE9UDC Frame Number MSB Fnmsb 24. Ufnhr Bit DefinitionsIsochronous Packet Error Endpoint 14 IPE14 UDC Frame Number Low Register UfnlrUDC Byte Count Register x UBCR2/4/7/9/12/14 Start of Frame Interrupt Mask SIMEndpoint x Byte Count BC UDC Endpoint 0 Data Register UDDR026. UBCR2/4/7/9/12/14 Bit Definitions UDC Endpoint x Data Register UDDR1/6/11 UDC Endpoint x Data Register UDDR2/7/1227. UDDR0 Bit Definitions 28. UDDR1/6/11 Bit DefinitionsUDC Endpoint x Data Register UDDR3/8/13 UDC Endpoint x Data Register UDDR4/9/1429. UDDR2/7/12 Bit Definitions 30. UDDR3/8/13 Bit DefinitionsUSB Device Controller Register Summary UDC Endpoint x Data Register UDDR5/10/1531. UDDR4/9/14 Bit Definitions 32. UDDR5/10/15 Bit DefinitionsUfnhr 33. USB Device Controller Register Summary Sheet 2Ufnlr 33. USB Device Controller Register Summary Sheet 3 AC’97 Controller Unit Signal Configuration Steps Example AC-linkExternal Interface to CODECs Name Direction Description summaryAC-link Digital Serial Interface Protocol Supported Data Stream Formats Sheet 1SDATAIN0 SDATAIN1 Channel Slots CommentsSupported Data Stream Formats Sheet 2 AC-link Audio Output Frame SdataoutSync AC-link Audio Output Frame Slot 0 Tag Phase Slot 1 Command Address PortSlot 2 Command Data Port Slot 3 PCM Playback Left ChannelSlot 1 Bit Definitions Slot 2 Bit DefinitionsAC-link Audio Input Frame Sdatain Slot 4 PCM Playback Right ChannelSlot 5 Modem Line Codec Slots 6-11 ReservedSync Input Slot 1 Bit Definitions Sheet 1 Slot 1 Status Address Port/SLOTREQ bitsBit Description Slot 2 Status Data Port Slot 3 PCM Record Left ChannelSlot 4 PCM Record Right Channel Slot 5 Optional Modem Line CodecAC-link Low Power Mode Powering Down the AC-linkSlots 7-11 Reserved Slot 12 I/O StatusWaking up the AC-link Wake up triggered by the CodecCold AC’97 Reset Warm AC’97 ResetAcunit Operation Wake Up Triggered by the AcunitInitialization 13-16 Intel PXA255 Processor Developer’s Manual Operational Flow for Accessing Codec Registers Clocks and Sampling FrequenciesReceive Fifo Errors Transmit Fifo ErrorsFIFOs Interrupts RegistersGlobal Control Register GCR GCR Bit Definitions Sheet 1Global Status Register GSR GCR Bit Definitions Sheet 2Warmrst ColdrstGSR Bit Definitions Sheet 1 Cdone SdoneRdcs Secres Prires SCR PCR Mint Point PiintGSR Bit Definitions Sheet 2 PCM-Out Control Register PocrPocr Bit Definitions Sheet 1 Pocr Bit Definitions Sheet 2 PCM-In Control Register Picr10. Picr Bit Definitions PCM-Out Status Register Posr PCMIn Status Register Pisr11. Posr Bit Definitions 12. Pisr Bit DefinitionsCodec Access Register CAR PCM Data Register Pcdr13. CAR Bit Definitions 14. Pcdr Bit DefinitionsMic-In Control Register Mccr Mic-In Status Register Mcsr15. Mccr Bit Definitions Mccr RegisterMic-In Data Register Mcdr 16. Mcsr Bit Definitions17. Mcdr Bit Definitions MicindatModem-Out Control Register Mocr Modem-In Control Register Micr18. Mocr Bit Definitions Mocr RegisterModem-Out Status Register Mosr Modem-In Status Register Misr19. Micr Bit Definitions 20. Mosr Bit DefinitionsModem Data Register Modr 21. Misr Bit Definitions22. Modr Bit Definitions ModemdatAccessing Codec Registers 11. Modem Transmit and Receive OperationProcessor Bit Physical 23. Address Mapping for Codec Registers Sheet 1Address for a Primary Secondary Audio Codec Modem Codec 23. Address Mapping for Codec Registers Sheet 2 13.9 AC’97 Register Summary 24. Register Mapping Summary13-36 Intel PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound I2S Controller GP32/SYSCLK GP29/SDATAINController Operation Disabling and Enabling Audio Replay Disabling and Enabling Audio RecordReceive Fifo Errors Transmit Fifo ErrorsSerial Audio Clocks and Sampling Frequencies Fifo and Memory Format 14.5.2 I2S and MSB-Justified Serial Audio FormatsSupported Sampling Frequencies Sysclk = Bitclk =I2S Data Formats 16 bits Registers Serial Audio Controller Global Control Register SACR0Special purpose Fifo Read/Write function SACR0 Bit DefinitionsSuggested Tfth and Rfth for DMA servicing Fifo Write/Read tableTfth and Rfth Values for DMA Servicing Efwr StrfSACR1 Bit Definitions EnlbfDrpl DrecSerial Audio Clock Divider Register Sadiv SASR0 Bit DefinitionsRFL TFLSadiv Bit Definitions Serial Audio Interrupt Clear Register SaicrSaicr Bit Definitions Serial Audio Interrupt Mask Register Saimr Serial Audio Data Register Sadr10. Saimr Bit Descriptions 11. Sadr Bit DescriptionsTransmit and Receive Fifo Accesses Through the Sadr 14.8 I2S Controller Register Summary12. Register Memory Map Address Register Description Paddr90 NameMultiMediaCard Controller MMC Data Token Format Command Token FormatSPI Data Token Format Mmcmd MmdatMMC Controller Functional Description CRCIntel PXA255 Processor Developer’s Manual 15-5 Signal Description MMC Controller ResetMMC Signal Description Card Initialization SequenceMMC Mode Error Detection SPI ModeClock Control Response Data Fifo Mmcres Data FIFOsReceive Data FIFO, Mmcrxfifo Transmit Data FIFO, Mmctxfifo Card Communication Protocol DMA and Program I/OBasic, No Data, Command and Response Sequence Mmcclkrt Mmcspi MmcrestoBlock Data Write Block Data Read Stream Data WriteBusy Sequence Stream Data ReadEnabling SPI Mode MultiMediaCard Controller OperationSPI Functionality Start and Stop ClockErase No Data Command and Response SequenceSingle Data Block Write Single Block Read Multiple Block Write Multiple Block ReadStream Write Stream ReadMMC Controller Registers Mmcstrpcl RegisterMMCStatus Register Mmcstat Mmcstrpcl Bit DefinitionsMmcstat Bit Definitions Sheet 1 StrpclMmcclkrt Register Mmcclkrt Mmcstat Bit Definitions Sheet 2Mmcclk Bit Definitions Mmcspi Register MmcspiMmcspi Bit Definitions Sheet 1 Mmcspi Bit Definitions Sheet 2 Mmccmdat Register MmccmdatMmccmdat Bit Definitions Sheet 1 Mmccmdat Bit Definitions Sheet 2 Mmcresto Register Mmcresto10. Mmcresto Bit Definitions Mmcrdto Register Mmcrdto 11. Mmcrdto RegisterReadto Specifies the length of time before a data read time-outMmcblklen Register Mmcblklen Mmcnob Register Mmcnob12. Mmcblklen Bit Definitions 13. Mmcnob Bit DefinitionsMmcprtbuf Register Mmcprtbuf Mmcimask Register Mmcimask14. Mmcprtbuf Bit Definitions 15. Mmcimask Bit Definitions Sheet 1Mmcireg Register Mmcireg 15. Mmcimask Bit Definitions Sheet 2Mmcimask Register MultiMediaCard Controller 4 3 2 116. Mmcireg Bit Definitions 18. Command Index Values Sheet 1 CMD Comm Mode Abbreviation IndexMmccmd Register Mmccmd 17. Mmccmd Register18. Command Index Values Sheet 2 18. Command Index Values Sheet 3 Mmcargh Register MmcarghMmcargl Register Mmcargl 19. Mmcargh Bit DefinitionsMmcres Fifo 21. MMCRES, Fifo Entry22. MMCRXFIFO, Fifo Entry ResponsedataMultiMediaCard Controller Register Summary 23. MMCTXFIFO, Fifo Entry24. MMC Controller Registers Sheet 1 Writedata24. MMC Controller Registers Sheet 2 Features Network SSP Serial PortSSP Serial Port I/O Signals Processor and DMA Fifo AccessOperation Trailing Bytes in the Receive Fifo Data Formats16-4 Intel PXA255 Processor Developer’s Manual TI Synchronous Serial Protocol* Details SPI Protocol Details Serial Clock Phase SPH Motorola SPI* Frame Protocol multiple transfers16-8 Intel PXA255 Processor Developer’s Manual Microwire* Protocol Details PSP Details Programmable Serial Protocol multiple transfers Programmable Serial Protocol PSP Parameters SspspscmodeSspspsfrmp SspspstrtdlyHi-Z on Ssptxd 11. TI SSP with SSCRTTE=1 and SSCRTTELP=0Motorola SPI Programmable Serial Protocol 16-16 Intel PXA255 Processor Developer’s Manual Fifo Operation Baud-Rate Generation16-18 Intel PXA255 Processor Developer’s Manual SSCR0 Bit Definitions Sheet 1 SSCR0SCR SSE FRF DSSSSCR0 Bit Definitions Sheet 2 Edss SCR SSEData Size Select Edss DSSTtelp TTE Ebcei Sclkdir Sfrmdir ScfrSSCR1 SPH SPO LBM TIE RIESSP Programmable Serial Protocol Register Sspsp Sspsp Bit Definitions Sheet 1 SSP Time Out Register Ssto SSP Interrupt Test Register SsitrSspsp Bit Definitions Sheet 2 Ssto Bit DefinitionsTest Receive Fifo Service Request Trfs Test Transmit Fifo Service Request TtfsSsitr Bit Definitions SsitrSssr Bit Definitions Sheet 1 SssrBCE CSS TUR TintSssr Bit Definitions Sheet 2 Transmit Fifo Service Request Sssr Bit Definitions Sheet 3SSP Busy Receive Fifo not EmptyNetwork SSP Serial Port Register Summary 10. Nssp Register Address MapSsdr Data TRANSMIT/RECEIVE Data16-30 Intel PXA255 Processor Developer’s Manual Hardware Uart Hardware Uart Uart Signal Descriptions Operation17-4 Intel PXA255 Processor Developer’s Manual Fifo Interrupt Mode Operation Fifo Polled Mode OperationCharacter Timeout Interrupt Receive InterruptDMA Receive Programming Errors Fifo DMA Mode OperationDMA Error Handling Autoflow Control Removing Trailing Bytes In DMA ModeAuto-Baud-Rate Detection 17-8 Intel PXA255 Processor Developer’s Manual Intel PXA255 Processor Developer’s Manual 17-9 Receive Buffer Register RBR Transmit Holding Register THRDivisor Latch Registers DLL and DLH Bit Reserved Byte Bits Name Description 318Interrupt Enable Register IER Divisor Latch Register High DLH Bit DefinitionsDLL DLH0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name Physical Address Interrupt Enable Register IER? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description Interrupt Identification Register IIR IIRABL TOD IID NIPPriority Type Source Reset Control Interrupt Identification Register Decode Sheet 10x41600008 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0Interrupt Identification Register Decode Sheet 2 Fifo Control Register FCR10. FCR Bit Definitions Sheet 1 10. FCR Bit Definitions Sheet 2 Receive Fifo Occupancy Register for11. for Bit Definitions Auto-Baud Control Register ABR Auto-Baud Count Register ACR12. ABR Bit Definitions ABTLine Control Register LCR 13. ACR Bit Definitions14. LCR Bit Definitions Sheet 1 ACRLine Status Register LSR 14. LCR Bit Definitions Sheet 2Line Control Register LCR PXA255 Processor Hardware Uart Dlab Stkyp EPS PEN STB WLS0x41600014 Bit 15. LSR Bit Definitions Sheet 1? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits Modem Control Register MCR 15. LSR Bit Definitions Sheet 2Line Status Register LSR PXA255 Processor Hardware Uart 0 0 0 0 Bits Name Description0x41600010 Bit Reset ? ? ? ? ? ? ? Bits 16. MCR Bit Definitions Sheet 1Physical Address Modem Control Register MCR AFE16. MCR Bit Definitions Sheet 2 Modem Status Register MSR17. MSR Bit Definitions Sheet 1 Scratchpad Register SCR Infrared Selection Register ISR17. MSR Bit Definitions Sheet 2 18. SCR Bit DefinitionsHardware Uart Register Summary 19. ISR Bit Definitions20. Hwuart Register Locations Sheet 1 Rxpl Txpl Xmode Rcveir Xmitir20. Hwuart Register Locations Sheet 2 Intel PXA255 Processor Developer’s Manual 17-27