Intel PXA255 manual Block Data Read, Stream Data Write

MultiMediaCard Controller

15.3.2.2Block Data Read

In a single block data read, a block of data is read from a card. In a multiple block read, the controller performs multiple single block read data transfers on the MMC bus.

After turning the clock on to start the command sequence, the software must program the DMA to empty the MMC_RXFIFO (read 32 bytes). The software will continue the process of emptying the FIFO until all of the data has been read from the FIFO. The software must then wait for the transmission to complete by waiting for the MMC_I_REG[DATA_TRAN_DONE] interrupt. The software can then read the status register, MMC_STAT, to verify the status of the transaction.

For multiple block reads, The MultiMediaCard System Specification specifies that the card will continue to send blocks of data until the stop transmission command is received. After the controller has received the number of bytes specified in the MMC_NOB register, the controller will stop receiving data. After the MMC_I_REG[DATA_TRAN_DONE] interrupt is detected, the software must set up the controller to send the stop transmission command, CMD12. Consult The MultiMediaCard System Specification for a description of the stop transmission command.

If both receive FIFOs become full during the data transmission, the controller turns the clock off. Once the software empties the FIFO to which it is connected, the controller turns the clock back on.

In a block data read, the following parameters must be specified:

•The data transfer is a read.

•The block length, if the block length is different from the previous block data transfer or this is the first time that the parameter is being specified.

•The number of blocks to be transferred.

•The receive data time-out period.

The controller will mark the data transaction as timed out if data is not received before the time-out period. The delay for the time-out period is defined as:

(MMC_RDTO[READ_TO]) ⋅ (128) Time-out Delay = -----------------------------------------------------------------------------------------sec

107

The software is required to calculate this value and write the appropriate value into the MMC_RDTO register.

15.3.2.3Stream Data Write

The stream data write looks like the single block write except a stop transmission command is sent in parallel with the last six bytes of data.

After turning the clock on to start the command sequence, the software must start the process of filling the MMC_TXFIFO and starting the clock as describe in Section 15.3.2.1. The software must then wait for the MMC_I_REG[STOP_CMD] interrupt. This interrupt indicates that the MMC controller is ready for the stop transmission command. The software must then stop the clock, write the registers for a stop transmission command, and then start the clock. At this point, the software must wait for the MMC_I_REG[DATA_TRAN_DONE] and MMC_I_REG[PRG_DONE] interrupts.

Intel® PXA255 Processor Developer’s Manual 15-15