Intel PXA255 manual Receive Fifo Occupancy Register for, FCR Bit Definitions Sheet 2

Hardware UART

Table 17-10. FCR Bit Definitions (Sheet 2 of 2)

			Physical Address									FIFO Control Register (FCR)										PXA255 Processor Hardware UART
				0x4160_0008
Bit
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0

Reset ? ? ? ? ? ? ? ?

Bits Name

1RESETRF

0TRFIFOE

reserved ITL reserved TIL RESETTF RESETRF TRFIFOE

?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? ? 0 0 0 0

Description

Reset Receiver FIFO – When RESETRF is set to 1, all the bytes in the receiver FIFO are cleared. The DR bit in the LSR is reset to 0. All the error bits in the FIFO and the FIFOE bit in the LSR are cleared. Any error bits, OE, PE, FE or BI, that had been set in LSR are still set. The receiver shift register is not cleared. If the IIR had been set to received data available, it is cleared.

0 = Writing 0 has no effect

1 = The receiver FIFO is cleared

Transmit and Receive FIFO Enable – TRFIFOE enables/disables the transmitter and receiver FIFOs. When TRFIFOE = 1, both FIFOs are enabled (FIFO Mode). When TRFIFOE = 0, the FIFOs are both disabled (non-FIFO Mode). Writing a 0 to this bit clears all bytes in both FIFOs. When changing from FIFO mode to non-FIFO mode and vice versa, data is automatically cleared from the FIFOs. This bit must be 1 when other bits in this register are written or the other bits are not programmed.

0 = FIFOs are disabled

1 = FIFOs are enabled

17.5.7Receive FIFO Occupancy Register (FOR)

The FOR, shown in Table 17-11, shows the number of bytes currently remaining in the receive FIFO. It can be used by the processor to determine the number of trailing bytes to remove. The FOR is incremented once for each byte of data written to the receive FIFO and decremented once for each byte read.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 17-11. FOR Bit Definitions

			Physical Address								FIFO Occupancy Register (FOR)											PXA255 Processor Hardware UART
				0x4160_0024
Bit
	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
												reserved																Byte Count
Reset	?	? ? ? ? ? ? ?							? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0																		0	0	0	0	0	0
		Bits				Name													Description
		31:7				—			reserved
		6:0			Byte Count				Number of bytes (0-64) remaining in the receiver FIFO

17-16 Intel® PXA255 Processor Developer’s Manual