Intel PXA255 manual Power Manager General Configuration Register Pcfr, Pcfr Bit Definitions, Opde

Clocks and Power Manager

3.5.2Power Manager General Configuration Register (PCFR)

The PCFR contains bits used to configure functions in the processor. When the OPDE bit is set, it allows the 3.6864 MHz oscillator to be disabled during Sleep Mode. The OPDE bit is cleared in Hardware, Watchdog, and GPIO Resets. The Float PCMCIA (FP) and Float Static Memory (FS) bits control the state of the PCMCIA control pins and the static memory control pins during Sleep Mode.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 3-8. PCFR Bit Definitions

				0x40F0_001C											PCFR								Clocks and Power Manager
Bit	31 30 29 28				27	26 25 24 23 22 21 20							19 18 17 16 15 14 13 12								11	10	9	8	7	6	5	4	3	2	1	0
															Reserved															FS	FP	OPDE
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0
		Bits				Name													Description
		[31:3]					—		Reserved.
									Read undefined and must always be written with zeroes.
									Float Static Chip Selects during Sleep Mode.
									0 = Static Chip Select pins are not floated in Sleep Mode. nCS[5:1] are driven to the
			2			FS				state of the appropriate PGSR register bits. nCS[1], nWE, and nOE are driven high.
									1 = Static Chip Select pins are floated in Sleep Mode. The pins nCS[5:0], nWE, and
										nOE are affected.

Cleared on Hardware, Watchdog, and GPIO Resets.

Float PCMCIA controls during Sleep Mode.

		0 =	PCMCIA pins are not floated in Sleep Mode. They are driven to the state of the
			appropriate PGSR register bits.
1	FP	1 =	The PCMCIA signals: nPOE, nPWE, nPIOW, nPIOR, and nPCE[2:1] are floated in
			Sleep Mode. nPSKTSEL and nPREG are derived from address signals and assume
			the state of the address bus during Sleep Mode.

Cleared on Hardware, Watchdog, and GPIO Resets.

		3.6864 MHz oscillator power-down enable.
		If the 32.7686 kHz crystal is disabled because the OON bit in the Oscillator
		Configuration Register is 0, OPDE is ignored and the 3.6864 MHz oscillator is not
0	OPDE	disabled.
		0 = Do not stop the oscillator during Sleep Mode.
		1 = Stop the 3.6864 MHz oscillator during Sleep Mode.
		Cleared on Hardware, Watchdog, and GPIO Resets.

3-24 Intel® PXA255 Processor Developer’s Manual