Intel PXA255 manual Synchronous Static Memory Interface

Memory Controller

Figure 6-11. SDRAM 4-Beat Write / 4-Write Same Bank, Same Row

0ns

25ns

50ns

75ns

100ns

tRP = 2 clks tRCD = 2 clks tRAS = 2 clks CL = 2 clks

tRCDCL

SDCLK

nSDCS

MA[24:0] row col col

nSDRAS

nSDCAS

nWE

DATA 0 1 2 3 4 5 6 7

DQM[3:0] mask0 mask1 mask2 mask3 mask4 mask5 mask6 mask7

6.6Synchronous Static Memory Interface

The synchronous static memory interface supports SMROM and non-SDRAM-like Flash memories. The synchronous static memory can be configured for any of the nCS[3:0] signals. Chip Select 0 must be used for boot memory. Synchronous static memories in bank pairs 1/0 or 3/2 must be set to the same timing.

If any of the nCS[3:0] banks are configured for Synchronous Static Memory via SXCNFG[SXENx], the corresponding half-words of MSC0 (see Section 6.7.3) and MSC1, except the data width in MSCx[RBWx], are ignored.

6.6.1Synchronous Static Memory Configuration Register (SXCNFG)

SXCNFG controls all synchronous static memory. SXCNFG[15:0] configures chip select signals 0 and 1. SXCNFG[31:16] configures chip select signals 2 and 3.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

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