Memory Controller

Figure 6-31. Alternate Bus Master Mode

Processor

Memory

Controlle

MBREQ

 

MBGNT

 

 

 

 

GPIO

Block

EXTERNAL SYSTEM

SDCKE<1>

 

SDCLK<1>

 

nSDCS(0)

 

nSDRAS

External

nSDCAS

SDRAM

nWE

Bank 0

 

MA[25:0]

 

DQM[3:0]

 

MD[31:0]

 

 

Companion

 

Chip

GPIO<13> (MBGNT)

 

GPIO<14> (MBREQ)

 

Figure 6-32. Variable Latency IO

 

EXTERNAL SYSTEM

 

Processor

 

 

 

nCS(0,1,2,3,4,5)

 

 

nOE

 

 

nPWE

 

Memory

MA[25:0]

Companion

Controller

DQM[3:0]

Chip

 

 

 

 

MD[31:0]

 

 

RDY

 

Intel® PXA255 Processor Developer’s Manual

 

6-71

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Image 253
Intel PXA255 manual Alternate Bus Master Mode, Variable Latency IO