MultiMediaCard Controller

15.5.10MMC_PRTBUF Register (MMC_PRTBUF)

MMC_PRTBUF, shown in Table 15-14, is used when MMC_TXFIFO is partially written. The FIFOs swap when either FIFO is full (32 bytes) or the MMC_PRTBUF register is set to a 1.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 15-14. MMC_PRTBUF Bit Definitions

 

 

 

Physical Address

 

 

 

MMC_PRTBUF Register

 

 

 

MultiMediaCard Controller

 

 

 

 

 

0x4110_0024

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

reserved

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

31:1

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Buffer Partially Full

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

BUF_PART_F

0 – Buffer is not partially full.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ULL

 

1 – Buffer is partially full and must be swapped to the other transmit buffer

 

 

 

 

 

 

 

 

 

 

 

Software must clear this bit before sending the next command.

0

BUF PART_ FULL_

0

15.5.11MMC_I_MASK Register (MMC_I_MASK)

MMC_I_MASK, shown in Table 15-15, masks off the various interrupts when set to a 1.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 15-15. MMC_I_MASK Bit Definitions (Sheet 1 of 2)

Physical Address

MMC_I_MASK Register

MultiMediaCard Controller

0x4110_0028

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

reserved

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

Bits

 

 

Name

 

 

 

 

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

31:7

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

 

TXFIFO_WR_

Transmit FIFO Write Request

 

 

 

 

 

 

 

 

 

 

 

 

 

 

REQ

 

0 –

Not masked

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1 –

 

Masked

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

6

5

4

3

2

1

0

TXFIFO WR REQ

 

RXFIFO RD REQ

 

CLK IS OFF

 

STOP CMD

 

END CMD RES

 

PRG DONE

 

DATA TRAN DONE

 

 

 

 

 

 

1

1

1

1

1

1

1

15-30

Intel® PXA255 Processor Developer’s Manual

Page 534
Image 534
Intel PXA255 manual Mmcprtbuf Register Mmcprtbuf, Mmcimask Register Mmcimask, Mmcprtbuf Bit Definitions