Intel PXA255 Clocks and Sampling Frequencies, Operational Flow for Accessing Codec Registers

AC’97 Controller Unit

13.6.2Trailing bytes

Trailing bytes in the transmit and receive FIFOs are handled as follows:

If the transmit buffers do not have 32-byte resolution, the trailing bytes in the Transmit FIFO are not transmitted. A transmit buffer must be padded with zeroes if it is smaller than a multiple of 32 bytes. Regardless of burst size, the DMA descriptor length must be a multiple of 32 bytes to prevent audio artifacts from being introduced onto the AC-link.

If the CODEC transmitted data has a total buffer size smaller than a multiple of 32 bytes, zeroes are recorded. A receive DMA request is made when the receive FIFO is half-full.

13.6.3Operational Flow for Accessing CODEC Registers

Software accesses the CODEC registers by translating a 32-bit processor physical address to a 7-bit CODEC address. For details regarding the address translation, refer to Section 13.8.3.17.

Software must read the CODEC Access Register (CAR) to lock the AC-link. The AC-link is free if the CAIP bit of the CAR is zero. For details about the CAR, refer to Table 13-13.

A read access to the CAR sets the CAIP bit. The ACUNIT clears the CAIP bit when the CODEC- write or CODEC-read operation completes. Software can also clear the CAIP bit by writing a zero to it.

After it locks the AC-link, software can write or read a CODEC register using the appropriate processor physical address.

The ACUNIT sets the CDONE bit of the GSR to one after the completion of a CODEC write operation. For details, refer to Table 13-8. Software clears this bit by writing a 1 to it.

To read a CODEC, the software must complete the following steps:

1.Software issues a dummy read to the CODEC register. The ACUNIT responds to this read operation with invalid data. The ACUNIT then initiates the read access across the AC-link.

2.When the CODEC read operation completes, the ACUNIT sets the SDONE bit of the GSR to one. For details, refer to Table 13-8. Software clears this bit by writing a 1 it.

3.Software repeats the read operation as detailed in Step 1. The ACUNIT now returns the data sent by the CODEC. The second read operation also initiates a read access across the AC-link.

4.The ACUNIT times-out the read operation if the CODEC fails to respond in four SYNC frames. In this case, the second read operation returns a timed-out data value of 0x0000_FFFF.

13.7Clocks and Sampling Frequencies

By default, the ACUNIT transmits and receives data at a sampling frequency of 48 kHz. It can, however, sample data at frequencies less than 48 kHz if the CODEC supports on-demand slot requests. The CODEC in this case executes a certain algorithm and informs the ACUNIT not to transmit valid data in certain frames. For example, if the ACUNIT sends out 480 frames, and the CODEC instructs the ACUNIT not to send valid data in 39 of those 480 frames, the CODEC would have in effect sampled data at 44.1 kHz. When the CODEC transmits data (ACUNIT-receive mode), it can use the same algorithm to transmit valid frames with some empty ones mixed in between.

Intel® PXA255 Processor Developer’s Manual 13-17