System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

SDATA_OUT/

 

AC97 Audio Port data out. (output) Output from the

Pulled High -

 

ICOCZ

PXA255 processor to Codecs 0 and 1.

Note [3]

GPIO[30]

Note[1]

 

I2S data out. (output) Output line for the I2S Controller.

 

 

 

 

 

 

 

AC97 Audio Port sync signal. (output) Frame sync

 

 

SYNC/

ICOCZ

signal for the AC97 Controller.

Pulled High -

Note [3]

GPIO[31]

I2S sync. (output) Frame sync signal for the I2S

Note[1]

 

 

 

 

Controller.

 

 

 

 

 

 

 

nACRESET

OC

AC97 Audio Port reset signal. (output)

Driven Low

Driven Low

I2C Controller Pins

 

 

 

SCL

ICOCZ

I2C clock. (bidirectional)

Hi-Z

Hi-Z

SDA

ICOCZ

I2C data. (bidirectional).

Hi-Z

Hi-Z

PWM Pins

 

 

 

 

PWM[1:0]/

ICOCZ

Pulse Width Modulation channels 0 and 1. (outputs)

Pulled High -

Note [3]

GPIO[17:16]

Note[1]

 

 

 

DMA Pins

 

 

 

 

DREQ[1:0]/

 

DMA Request. (input) Notifies the DMA Controller that

Pulled High -

Note [3]

ICOCZ

an external device requires a DMA transaction. DREQ[1]

GPIO[19:20]

Note[1]

 

is GPIO[19]. DREQ[0] is GPIO[20].

 

 

 

 

 

GPIO Pins

 

 

 

 

GPIO[1:0]

ICOCZ

General Purpose I/O. Wakeup sources on both rising

Pulled High

Note [3]

and falling edges on nRESET.

Note [1]

 

 

 

 

 

 

 

 

GPIO[14:2]

ICOCZ

General Purpose I/O. More wakeup sources for sleep

Pulled High

Note [3]

mode.

Note [1]

 

 

 

 

 

 

 

 

GPIO[22:21]

ICOCZ

General Purpose I/O. Additional General Purpose I/O

Pulled High

Note [3]

pins.

Note [1]

 

 

 

Crystal and Clock Pins

 

 

 

PXTAL

IA

3.6864 Mhz crystal input. No external caps are required.

Note [2]

Note [2]

 

 

 

 

 

PEXTAL

OA

3.6864 Mhz crystal output. No external caps are

Note [2]

Note [2]

required.

 

 

 

 

 

 

 

 

 

TXTAL

IA

32 Khz crystal input. No external caps are required.

Note [2]

Note [2]

 

 

 

 

 

TEXTAL

OA

32 Khz crystal output. No external caps are required.

Note [2]

Note [2]

 

 

 

 

 

L_DD[12]/

 

LCD display data. (output) Transfers pixel information

Pulled High

 

ICOCZ

from the LCD Controller to the external LCD panel.

Note [3]

GPIO[70]

Note [1]

 

RTC clock. (output) Real time clock 1 Hz tick.

 

 

 

 

 

 

 

 

 

 

 

 

LCD display data. (output) Transfers the pixel

 

 

L_DD[13]/

 

information from the LCD Controller to the external LCD

Pulled High -

 

ICOCZ

panel.

Note [3]

GPIO[71]

Note[1]

 

3.6864 MHz clock. (output) Output from 3.6864 MHz

 

 

 

 

 

 

 

oscillator.

 

 

 

 

 

 

 

L_DD[14]/

 

LCD display data. (output) Transfers pixel information

Pulled High -

 

ICOCZ

from the LCD Controller to the external LCD panel.

Note [3]

GPIO[72]

Note[1]

 

32 kHz clock. (output) Output from the 32 kHz oscillator.

 

 

 

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

2-15

Page 45
Image 45
Intel manual Pin & Signal Descriptions for the PXA255 Processor Sheet 7