Intel PXA255 Auto-Baud Control Register ABR, Auto-Baud Count Register ACR, ABR Bit Definitions

Hardware UART

17.5.8Auto-Baud Control Register (ABR)

The ABR, shown in Table 17-12, controls the functionality and options for auto-baud-rate detection within the UART. Through this register, users can enable or disable the auto-baud lock interrupt, direct either the processor or UART to program the final baud rate in the Divisor Latch registers, and choose between the two methods used to calculate the final baud rate.

The auto-baud circuitry counts the number of clocks in the start bit and writes this count into the Auto-Baud Count register (ACR – refer to Section 17.5.9). It then interrupts the processor if ABR[ABLIE] is set. It also automatically programs the Divisor Latch registers (DLL and DLH – refer to Section 17.5.3) if ABR[ABUP] bit is set.

See Section 17.4.4 for more information on auto-baud rate.

Note: Auto-baud rate detection is not supported with slow infrared Mode.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 17-12. ABR Bit Definitions

Physical Address	Autobaud Control Register (ABR)	PXA255 Processor Hardware UART
0x4160_0028

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Reset ? ? ? ? ? ? ?

Bits	Name
31:4	—
3	ABT

2 ABUP

1ABLIE

0ABE

reserved ABT ABUP ABLIE ABE

?? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0

Description

reserved

AutoBaud Table. Uses a table to select low-speed baud rates instead of a formula. Only valid if ABR[ABUP] is set.

0 = Table used to calculate baud rates which limits UART to choosing common baud rates as shown in Section 17.4.4, “Auto-Baud-Rate Detection” on page 17-7

1 = Formula used to calculate baud rates allowing all possible baud rates to be chosen by UART.

AutoBaud UART Program. Controls if the UART automatically programs DLL and DLH or if the processor must program DLL and DLH based on the results in the ACR.

0 = Processor Programs Divisor Latch registers

1 = UART Programs Divisor Latch registers Autobaud Lock Interrupt Enable.

0 = Autobaud Lock Interrupt disabled (Source IIR[ABL])

1 = Autobaud Lock Interrupt enabled (Source IIR[ABL])

Autobaud Enable.

0 = Autobaud Disabled

1 = Autobaud Enabled

17.5.9Auto-Baud Count Register (ACR)

The ACR, shown in Table 17-13, stores the number of 14.7456 MHz clock cycles within a start bit pulse. This value is then used by the processor or the UART to calculate the baud rate. If auto-baud mode (ABR[ABE] – Section 17.5.8) and auto-baud interrupts (ABR[ABLIE]) are enabled, the UART interrupts the processor with the auto-baud lock interrupt (IIR[ABL] – Section 17.5.5) after it has written the count value into the ACR. The value is written regardless of the state of the auto- baud UART program bit (ABR[ABUP]).

Intel® PXA255 Processor Developer’s Manual 17-17