Manuals / Intel / Home Audio / Speaker System

Intel PXA255 manual Ficp Operation, Ficp Signal Description

Models: PXA255

1 600

Page 387

Fast Infrared Communication Port

The Fast Infrared Communications Port (FICP) for the PXA255 processor operates at half-duplex and provides direct connection to commercially available Infrared Data Association (IrDA) compliant LED transceivers. The FICP is based on the 4-Mbps IrDA standard and uses four- position pulse modulation (4PPM) and a specialized serial packet protocol developed for IrDA transmission. To support the standard, the FICP has:

•A bit encoder/decoder,

•A serial-to-parallel data engine

•A transmit FIFO 128 entries deep and 8 bits wide

•A receive FIFO 128 entries deep and 11 bits wide

The FICP shares GPIO pins for transmit and receive data with the Standard UART. Only one of the ports can be used at a time. To support a variety of IrDA transceivers, both the transmit and receive data pins can be individually configured to communicate using normal or active low data.

11.1Signal Description

The FICP signals are IRRXD and IRTXD. Table 11-1describes each signal’s function. Most IrDA transceivers also have enable and speed pins. Use GPIOs to enable the transceiver and select the speed. See Chapter 4, “System Integration Unit” for more information.

Table 11-1. FICP Signal Description

Signal Name	Input/Output	Description

IRRXD	Input	Receive pin for FICP

IRTXD	Output	Transmit pin for FICP

11.2FICP Operation

The FICP is disabled and does not have control of the port’s pins after a reset. Before software enables the FICP for high-speed operation, it must set the control registers to reflect the desired operating mode. After the control registers are set, software can either preload the FICP’s transmit FIFO with up to 128 bytes, or leave the FIFO empty and use the DMA to service it after the FICP is enabled. Once the FICP is enabled, transmit/receive data can be sent on the transmit and receive pins.

The transmit/receive data is modulated according to the 4PPM IrDA standard and converted to serial or parallel data. The modulation technique and the frame format are discussed in the sections that follow.

Intel® PXA255 Processor Developer’s Manual

11-1

Page 387

Image 387

Intel PXA255 manual Ficp Operation, Ficp Signal Description

Contents

Intel PXA255 Processor Intel PXA255 Processor Developer’s Manual Contents Power Manager General Configuration Register Pcfr Contents Expansion Card Interface Timing Diagrams and Parameters DMA 10-1 11-1 12.6 14.3 15.5 Figures BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF = 10-25 Tables Clocks Manager Register Summary Sxcnfg 10-6 10-8 12-26 15-7 Date Revision Description Revision HistoryXxiv System Integration Features Intel XScale Microarchitecture FeaturesClocks and Power Controllers Memory ControllerUniversal Serial Bus USB Client Inter-IC Sound I2S Controller DMA Controller DmacLCD Controller 6 AC97 ControllerUARTs Synchronous Serial Protocol Controller SspcInter-Integrated Circuit I2C Bus Interface Unit GpioInterrupt Control OS TimersReal-Time Clock RTC Pulse-Width Modulator PWMIntroduction Overview System ArchitectureCoprocessor 7 Register 4 Psfs Bit Intel XScale Microarchitecture Implementation OptionsCoprocessor 15 Register 0 ID Register Definition Coprocessor 14 Register 6 and 7- Clock and Power ManagementCPU Core Fault Register Bit Definitions Coprocessor 14 Registers 0-3 Performance MonitoringARM ID Jtag ID Coprocessor 15 Register 1 P-BitID Bit Definitions PXA255 Processor ID ValuesI/O Ordering SemaphoresInterrupts ICP ResetUnit Sleep Mode Gpio Reset Watchdog Reset Hard Reset USBSelecting Peripherals vs. General Purpose I/O Internal RegistersProcessor Pin Types Power on Reset and Boot OperationPower Management Pin ListPin Name Type Signal Descriptions Reset State Sleep State Pin & Signal Descriptions for the PXA255 Processor Sheet 1Pin & Signal Descriptions for the PXA255 Processor Sheet 2 Psktsel Pin & Signal Descriptions for the PXA255 Processor Sheet 3Pin & Signal Descriptions for the PXA255 Processor Sheet 4 Pin & Signal Descriptions for the PXA255 Processor Sheet 5 Pin & Signal Descriptions for the PXA255 Processor Sheet 6 Pin & Signal Descriptions for the PXA255 Processor Sheet 7 Pwren Pin & Signal Descriptions for the PXA255 Processor Sheet 8Bootsel Rtcclk IcoczPin Description Notes Sheet 1 Pin & Signal Descriptions for the PXA255 Processor Sheet 9Pin Description Notes Sheet 2 Memory MapMemory Map Part One From 0x80000000 to 0xFFFF Ffff Memory Map Part Two From 0x00000000 to 0x7FFF Ffff Unit Address Register Symbol Register Description System Architecture Register SummarySystem Architecture Register Address Summary Sheet 1 System Architecture Register Address Summary Sheet 2 System Architecture Register Address Summary Sheet 3 System Architecture Register Address Summary Sheet 4 Unit System Architecture Register Address Summary Sheet 5System Architecture Register Address Summary Sheet 6 Unit Address System Architecture Register Address Summary Sheet 7System Architecture Register Address Summary Sheet 8 System Architecture Register Address Summary Sheet 9 System Architecture Register Address Summary Sheet 10 System Architecture Register Address Summary Sheet 11 System Architecture Register Address Summary Sheet 12 Clock Manager Introduction Clocks and Power ManagerClock Manager Power Manager IntroductionFicp I2C MMC Retains Power in SleepPWM SSP OSTCore Phase Locked Loop 1 32.768 kHz Oscillator2 3.6864 MHz Oscillator Sdram 4 95.85 MHz Peripheral Phase Locked Loop5 147.46 MHz Peripheral Phase Locked Loop Core PLL Output Frequencies for 3.6864 MHz CrystalResets and Power Modes Hardware ResetClock Gating Watchdog Reset Behavior During Gpio Reset Gpio ResetCompleting a Watchdog Reset Invoking Gpio ResetEntering Turbo Mode Run ModeTurbo Mode Completing Gpio ResetEntering Idle Mode Idle ModeBehavior in Turbo Mode Exiting Turbo ModePreparing for a Frequency Change Sequence Behavior in Idle ModeExiting Idle Mode Frequency Change SequenceBehavior During the Frequency Change Sequence Invoking the Frequency Change SequenceCompleting the Frequency Change Sequence 8 33-MHz Idle ModeBehavior in 33-MHz Idle Mode Entering 33-MHz Idle ModeSleep Mode Exiting 33-MHz Idle ModeSleep Mode External Voltage Regulator Requirements Entering Sleep Mode Preparing for Sleep ModeClocks and Power Manager Exiting Sleep Mode Behavior in Sleep ModeClocks and Power Manager Idle Power Mode SummaryPower Mode Entry Sequence Table Power Mode Exit Sequence Table Sheet 1Power Mode Exit Sequence Table Sheet 2 Power Mode Supply Source Module Turbo Run Power Manager RegistersIdae Power Manager Control Register PmcrPmcr Bit Definitions PmcrOpde Power Manager General Configuration Register PcfrPcfr Bit Definitions PcfrPwer Power Manager Wake-Up Enable Register PwerPwer Bit Definitions WertcPrer Power Manager Rising-Edge Detect Enable Register Prer10. Prer Bit Definitions 0x40F00010Pfer Power Manager Falling-Edge Detect Enable Register Pfer11. Pfer Bit Definitions 0x40F00014Pedr Power Manager Gpio Edge Detect Status Register Pedr12. Pedr Bit Definitions 0x40F00018RDH Power Manager Sleep Status Register Pssr13. Pssr Bit Definitions Sheet 1 PssrCPU VFS Power Manager Scratch Pad Register Pspr13. Pssr Bit Definitions Sheet 2 14. Pspr Bit Definitions15. Pmfw Register Bitmap and Bit Definitions Power Manager Fast Sleep Walk-up Configuration Register PmfwSS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 16. PGSR0 Bit Definitions17. PGSR1 Bit Definitions PGSR0PGSR2 Reset Controller Status Register RcsrBit Reset 0x40F00028 18. PGSR2 Bit DefinitionsRcsr Core Clock Configuration Register CccrClocks Manager Registers 19. Rcsr Bit DefinitionsMultiplier = 20. Cccr Bit Definitions0x41300000 Bit Reserved21. Cken Bit Definitions Sheet 1 Clock Enable Register CkenCKEN5 Description I2S Unit Clock Enable21. Cken Bit Definitions Sheet 2 CKEN8Coprocessor 14 Clock and Power Management Oscillator Configuration Register Oscc22. Oscc Bit Definitions Core Clock Configuration Register Cclkcfg 23. Coprocessor 14 Clock and Power Management Summary24. Cclkcfg Bit Definitions External Hardware Considerations Power Mode Register PwrmodePower-On-Reset Considerations Power Supply ConnectivityClocks Manager Register Locations Clocks and Power Manager Register SummaryDriving the Crystal Pins from an External Clock Source Power Manager Register Summary27. Power Manager Register Summary Gpio Operation General-Purpose I/OGpio Alternate Functions General-Purpose I/O Block DiagramGpio Alternate Functions Sheet 1 Gpio Alternate Functions Sheet 2 Gpio Alternate Functions Sheet 3 MMCCS0 ALTFN1OUTMbgnt ALTFN1OUT Gpio Register Definitions Gpio Alternate Functions Sheet 4Gpio Register Definitions Sheet 1 GPLR0 Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2Gpio Register Definitions Sheet 2 GPLR0 Bit DefinitionsGPLR1 Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2GPLR1 Bit Definitions GPLR2 Bit DefinitionsGPDR0 Bit Definitions GPDR1 Bit DefinitionsGPDR2 Bit Definitions PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 GPSR0 Bit Definitions10. GPSR1 Bit Definitions GPSR011. GPSR2 Bit Definitions 12. GPCR0 Bit Definitions13. GPCR1 Bit Definitions GPCR2 GPCR2 Bit Definitions15. GRER0 Bit Definitions 16. GRER1 Bit Definitions17. GRER2 Bit Definitions 18. GFER0 Bit Definitions 19. GFER1 Bit DefinitionsGFER2 Bit Definitions Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR2 21. GEDR0 Bit Definitions22. GEDR1 Bit Definitions GEDR2 GEDR2 Bit DefinitionsAF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0 24. GAFR0L Bit Definitions25. GAFR0U Bit Definitions GAFR0LGAFR1U 26. GAFR1L Bit Definitions27. GAFR1U Bit Definitions GAFR1LGAFR2U 28. GAFR2L Bit Definitions29. GAFR2U Bit Definitions GAFR2LInterrupt Controller Operation Interrupt ControllerInterrupt Controller Register Definitions Interrupt Controller Block DiagramIcmr Interrupt Controller Mask Register IcmrInterrupt Controller Level Register Iclr 30. Icmr Bit DefinitionsInterrupt Controller Control Register Iccr 31. Iclr Bit Definitions32. Iccr Bit Definitions 34. Icfp Bit Definitions 33. Icip Bit DefinitionsIS9 IS8 Interrupt Controller Pending Register Icpr35. Icpr Bit Definitions Sheet 1 IcprIS16 Network SSP Service Request Interrupt Pending35. Icpr Bit Definitions Sheet 2 IS14 IS13 IS12 IS11 IS10Bit Position Source Unit 35. Icpr Bit Definitions Sheet 336. List of First-Level Interrupts Sheet 1 System Integration UnitReal-Time Clock RTC Real-Time Clock Operation36. List of First-Level Interrupts Sheet 2 RTC Trim Register Rttr RTC Register DefinitionsRTC Alarm Register Rtar Rttr Bit Definitions38. Rtar Bit Definitions Rcnr RTC Counter Register RcnrRTC Status Register Rtsr 39. Rcnr Bit DefinitionsTrim Procedure Oscillator Frequency Calibration40. Rtsr Bit Definitions Rttr Value Calculations Trim Example #1 Measured Value Has No Fractional ComponentTrim Example #2 Measured Value Has a Fractional Component Maximum Error Calculation Versus RTC Accuracy Operating System OS TimerWatchdog Timer Operation OS Timer Register DefinitionsOS Timer Match Register 0-3 OSMRx OSMR3, OSMR2, OSMR1 OS Timer Interrupt Enable Register Oier41. OSMRx Bit Definitions 42. Oier Bit Definitions43. Ower Bit Definitions OS Timer Watchdog Match Enable Register OwerOS Timer Count Register Oscr OS Timer Status Register OssrOssr Bit Definitions 0x40A00014 Bit Reset ? ? ? ? ? ? ? ? BitsPulse Width Modulator Pulse Width Modulator Operation1.1 Interdependencies PWMn Block DiagramPWM Control Registers PWMCTRLn Reset SequencePower Management Requirements Register DescriptionsPrescale PWM Duty Cycle Registers PWMDUTYn46. PWMCTRLn Bit Definitions 0x40B00000Fdcycle Dcycle PWM Period Control Register PWMPERVALn47. PWMDUTYn Bit Definitions PWMDUTY0, PWMDUTY1Pulse Width Modulator Output Wave Example 48. PWMPERVALn Bit Definitions0x40B00008 System Integration Unit Register Summary Gpio Register Locations49. Gpio Register Addresses Sheet 1 OS Timer Register Locations Interrupt Controller Register LocationsReal-Time Clock Register Locations 52. OS Timer Register Addresses Sheet 2 Pulse Width Modulator Register Locations53. Pulse Width Modulator Register Addresses DMA Description Dmac Block DiagramSignal Signal Type To/From Definition In/Out Signal DescriptionsDREQ10 and PREQ370 Signals Dmac Signal ListDMA Channel Priority Scheme Dmairq SignalChannel Priority Channel Priority if all channels are running concurrentlyDMA Channel Priority No-Descriptor Fetch ModeDMA Descriptors Priority Schemes ExamplesNo-Descriptor Fetch Mode Channel State Descriptor Fetch ModeDMA Controller Servicing an Interrupt Channel StatesByte Transfer Order Read and Write OrderLittle Endian Transfers Trailing BytesServicing Internal Peripherals Transferring DataDcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg = Drcmr Quick Reference for DMA ProgrammingDMA Quick Reference for Internal Peripherals Sheet 1 DcmdBurst Size Source Servicing Companion Chips and External PeripheralsDMA Quick Reference for Internal Peripherals Sheet 2 Unit Function Fifo Address WidthDMA Controller Memory-to-Memory Moves Dint Bit Definitions Dmac RegistersDMA Interrupt Register Dint DMA Channel Control/Status Register DCSRxStopstate Endintr Startintr Buserrintr DCSRx Bit Definitions Sheet 1RUN ReqpendDCSRx Bit Definitions Sheet 2 Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0Chlnum DMA Request to Channel Map Registers DRCMRxDMA Descriptor Address Registers DDADRx DRCMRx Bit DefinitionsStop DMA Source Address RegistersDDADRx Bit Definitions Descriptor AddressSrcaddr DMA Target Address Registers DTADRx10. DSADRx Bit Definitions Source AddressTrgaddr DMA Command Registers DCMDx11. DTADRx Bit Definitions Target AddressSize 12. DCMDx Bit Definitions Sheet 1Incsrcaddr Endian WidthLength 12. DCMDx Bit Definitions Sheet 2Endian WidthExamples Example 1. How to set up and start a channelStruct longddadr longdsadr longdtadr shortlength shortdcmd 13. DMA Controller Register Summary Sheet 1 DMA Controller Register Summary13. DMA Controller Register Summary Sheet 2 13. DMA Controller Register Summary Sheet 3 13. DMA Controller Register Summary Sheet 4 13. DMA Controller Register Summary Sheet 5 Memory Controller Sdram Interface Overview Functional DescriptionStatic Memory Interface / Variable Latency I/O Interface 3 16-Bit PC Card / Compact Flash Interface Memory System ExamplesSdram Memory System Example Static Memory System Example Words Bits Memory AccessesDevice Transactions Bus Operation Burst SizeSdram Mdcnfg Register Mdcnfg Synchronous Dram Memory InterfaceReads and Writes Aborts and Nonexistent MemoryMdcnfg Bit Definitions Sheet 1 Mdcnfg Bit Definitions Sheet 2 DLATCH2 Mdcnfg Bit Definitions Sheet 3DNB2 DADDR2Mdmrs Bit Definitions Sheet 1 Sdram Mode Register Set Configuration Register MdmrsMdmrs Bit Definitions Sheet 2 Low-Power Sdram Mode Register Set Configuration RegisterMdmrslp Sdram Mdrefr Register MdrefrMdmrslp Register Bit Definitions 0X4800DRI Mdrefr Bit Definitions Sheet 1Mdrefr APD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PINMdrefr Bit Definitions Sheet 2 0 1 0 0 1 * * 11 1 1 1 1 1 1 Fixed-Delay or Return-Clock Data Latching Mdrefr Bit Definitions Sheet 3APD Number Chips Partition Size Sdram Memory OptionsSdram Addressing Modes Sample Sdram Memory Size Options# Bits ‘0’1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32 Col Data MA24102x13x10x16 ‘0’ Not Valid illegal addressing combination # Bits External Address pins at Sdram RAS TimeA10 MA24 MA23MA20 BA0BA1 BA0 MA24A11 A10 Memory Controller A12 Sdram Command Overview11. Sdram Command Encoding 12. Sdram Mode Register Opcode TableSdram Waveforms Data SdclkSDRAMreadsamebankdiffrow SDCLK1 SDCKE1 SDRAMwriteSynchronous Static Memory Interface Synchronous Static Memory Configuration Register SxcnfgSXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2 13. Sxcnfg Bit Definitions Sheet 10x4800001C SxcnfgSXLATCH0 Sxcnfg Bit Definitions Sheet 2SXLATCH2 SXRL2 SXCL2 SXEN213. Sxcnfg Bit Definitions Sheet 3 SXEN0 Smrom Memory OptionsSxcnfg Bit Definitions Sheet 4 SXCL0Smrom SXMRS2 Synchronous Static Memory Timing Diagrams16. Sxmrs Bit Definitions SxmrsSdclk Sdcke Non-SDRAM Timing Sxmem OperationMemclk SDCLK0 Mdrefr 17. Read Configuration Register Programming Values12shows the burst-of-eight read timing diagram Non-SDRAM Timing Flash Read Timing Diagram4.2 K3 Synchronous StrataFlash Reset Asynchronous Static MemoryStatic Memory Interface Sram Data Size MA0 DQM10 19 -Bit Bus Write Access20 -Bit Bus Write Access Data Size MA10 DQM3021 -Bit Byte Address Bits MA10 for Reads Based on DQM30 22 -Bit Byte Address Bit MA0 for Reads Based on DQM1023. SA-1111 Register Bit Definitions Asynchronous Static Memory Control Registers MSCx MSC2 24. MSC0/1/2 Bit Definitions Sheet 1MSC0 MSC1RRR1/3/5 RDN1/3/5 Reset RDF1/3/5 Bits Access Name24. MSC0/1/2 Bit Definitions Sheet 2 Sram 24. MSC0/1/2 Bit Definitions Sheet 3NWE NOE ROM InterfaceTiming Memory Clocks MSCxRTx Device NOEClkmem ROM Timing Diagrams and ParametersRDN+1 Sram Interface Overview Sram Timing Diagrams and Parameters20shows the timing for Sram writes Variable Latency I/O Vlio Interface Overview RDF+1+Waits RRR*2+1 Variable Latency I/O Timing Diagrams and ParametersRDF+1+Waits Flash Memory Interface Flash Memory Timing Diagrams and ParametersCMD Data 23. Asynchronous 32-Bit Flash Write Timing Diagram 2 WritesMCMEM0 Expansion Memory Timing Configuration Register16-Bit PC Card/Compact Flash Interface 26. MCMEM0/1 Bit DefinitionsMCATT1 27. MCATT0/1 Bit Definitions28. MCIO0/1 Bit Definitions MCATT0MCMEMxASST XASSTHOLD XASSTWAIT + 29. Card Interface Command Assertion Code TableCIT NOS Expansion Memory Configuration Register Mecr30. Mecr Bit Definition Mecr26 -Bit PC Card Memory Map 3 16-Bit PC Card Overview34. Attribute Memory Space Read Commands 31. Common Memory Space Write Commands32. Common Memory Space Read Commands 33. Attribute Memory Space Write Commands37 -Bit I/O Space Write Commands nIOIS16 = 38 -Bit I/O Space Read Commands nIOIS16 =External Logic for 16-Bit PC Card Implementation DIR Socket 29 -Bit PC Card Memory or I/O 16-Bit Half-word Access Expansion Card Interface Timing Diagrams and ParametersCompanion Chip Interface 30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device32. Variable Latency IO 31. Alternate Bus Master ModeAlternate Bus Master Mode Gpio Reset NVDDFAULT/nBATTFAULT with Pmcridae DisabledNVDDFAULT/nBATTFAULT with Pmcridae Enabled Bootdef Read-Only Register Bootdef Options and Settings for Boot MemoryAlternate Booting Boot Time DefaultsPKG Type Boot SEL 40. Bootdef Bitmap41. Valid Boot Configurations Based on Processor Type BootdefSxcnfg Boot-Time Configurations34. Smrom Boot Time Configurations and Register Defaults Memory Interface Reset and Initialization SmromMdrefr 03CA 7FFF Hardware, Watchdog, or Sleep Reset Operation 42. Memory Controller Pin Reset ValuesPin Name PXA255 Processor Reset Value Memory Controller 43. Memory Controller Register Summary Sheet 1 Gpio Reset ProcedurePhysical Address Symbol Register Name Memory Controller Register Summary43. Memory Controller Register Summary Sheet 2 LCD Controller LCD Controller FeaturesLCD Controller Block Diagram Pin Descriptions LCD Controller OperationPin Descriptions Enabling the ControllerInput FIFOs Resetting the ControllerDetailed Module Descriptions Disabling the ControllerTemporal Modulated Energy Distribution Tmed Dithering Lookup PaletteCompare Range for Tmed LCD Controller Pin Usage Output FIFOsActive Display Timing Pixel Data Pins LDDx6 DMA Passive Display TimingExternal Palette Buffer LCD External Palette and Frame BuffersPalette Buffer Format External Frame BufferBits Per Pixel Data Memory Organization 10 Bits Per Pixel Data Memory Organization Passive Mode FrameBufferSize = Functional Timing12. Passive Mode Start-of-Frame Timing Hsync Lbias VsyncLfclk Vsync Llclk Hsync Lbias Register DescriptionsLCD Controller Control Register 0 LCCR0 LCD Controller LDD LCD Controller Data Pin Utilization Sheet 1 LCD Controller Data Pin Utilization Sheet 2 Single Passive Screen Portion Pins0x44000000 Bit Reserved Reset X X X X X X X X X X XLCCR0 Bit Definitions Sheet 1 LCCR0PAS EFM IUM SFM LDM SDS CMS ENB LCD Controller Control Register 1 LCCR1LCCR0 Bit Definitions Sheet 2 QDM DIS DPDLCD Controller BLW LCD Controller Control Register 2 LCCR2LCCR1 Bit Definitions BLW ELW HSW PPLLCD Controller BFW LCD Controller Control Register 3 LCCR3LCCR2 Bit Definitions BFW EFW VSW LPPLCD Controller LCD Controller DPC BPP Reset X X X X 0 0 0LCCR3 Bit Definitions Sheet 1 0x4400000C Bit ReservedLCCR3 Bit Definitions Sheet 2 Reset X X XLCD Controller DMA Frame DescriptorsFDADR0 LCD DMA Frame Descriptor Address Registers FDADRxLCD DMA Frame Source Address Registers FSADRx FDADRx Bit DefinitionsLCD DMA Frame ID Registers FIDRx FSADRx Bit DefinitionsFIDRx Bit Definitions LCD DMA Command Registers LDCMDx PAL 10. LDCMDx Bit DefinitionsLDCMD0 LDCMD10 0 0 0 X X 0 Bits Name Description LCD DMA Frame Branch Registers FBRx11. FBRx Bit Definitions Bint BRALCD Controller Status Register Lcsr LCD Controller EOF IUU IUL ABC BER SOF LDD 0x44000038 Bit Reset X XLcsr Bit Definitions Sheet 1 X XSint BS EOF QD OU IUU IUL ABC BER SOF LDD LCD Controller Interrupt ID Register Liidr12. Lcsr Bit Definitions Sheet 2 13. Liicr Bit DefinitionsTRS Tmed RGB Seed Register Trgbr14. Trgbr Bit Definitions TBSTmed Control Register TCR LCD Controller Register Summary 15. TCR Bit Definitions16. LCD Controller Register Summary Sheet 1 16. LCD Controller Register Summary Sheet 2 LCD Controller Name Direction Description Signal DescriptionExternal Interface to Synchronous Serial Peripherals External Interface to CodecData Formats Data TransferSerial Data Formats for Transfer to/from Peripherals SSP Format Details LSB SPI Format DetailsSspsclk Sspsfrm Sspsclk Sspsfrm MSBSspsclk Sspsfrm Ssptxd Ssprxd Microwire Format DetailsParallel Data Formats for Fifo Storage National Microwire* Frame FormatBaud-Rate Generation Using Programmed I/O Data TransfersUsing DMA Data Transfers Fifo Operation and Data TransfersSSP Control Register 0 SSCR0 SSP Serial Port RegistersSCR Data Size Select DSSSSCR0 Bit Definitions SSP Control Register 0 SSCR0Synchronous Serial Port Enable SSE Frame Format FRFExternal Clock Select ECS SSP Control Register 1 SSCR1 Serial Clock Rate SCRSSCR1 Bit Definitions Sheet 1 SSCR1 Bit Definitions Sheet 2 Receive Fifo Interrupt Enable RIETransmit Fifo Interrupt Enable TIE Loop Back Mode LBMSerial Clock Phase SPH Serial Clock Polarity SPOSspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd Microwire Transmit Data Size MwdsTransmit Fifo Interrupt/DMA Threshold TFT Receive Fifo Interrupt/DMA Threshold RFTSSP Data Register Ssdr TFT and RFT Values for DMA ServicingSsdr Bit Definitions SSP Status Register Sssr RFL Transmit Fifo Not Full Flag TNFSssr Bit Definitions RFL TFL ROR RFS TFS BSY RNE TNFSSP Busy Flag BSY Transmit Fifo Service Request Flag TFSReceive Fifo Service Request Flag RFS Receive Fifo Not Empty Flag RNEAddress Abbreviation Full Name SSP Controller Register SummaryReceive Fifo Level RFL SSP Controller Register SummarySynchronous Serial Port Controller SCL I2C Signal DescriptionSignal Name Input/Output Description SDA2C Device Definition I2C Bus DefinitionsModes of Operation Mode DescriptionOperational Blocks 2 I2C Bus Interface ModesCondition Start and Stop Bus StatesStart and Stop Bit Definitions Stop StarStart Condition No Start or Stop ConditionStop Condition ACK Stop NAK ACK NAKStart ACKI2C Bus Operation Serial Clock Line SCL GenerationData and Addressing Management Addressing a Slave Device 3 I2C AcknowledgeArbitration PollingSDA Arbitration SCL ArbitrationArbitration Procedure of Two Masters 2C Master Mode Definition Action Operation Master OperationsMaster Transactions Sheet 1 Master Transactions Sheet 2 Master-Receiver Read from Slave-Transmitter Slave OperationsSlave Transactions 2C Slave Action Mode Definition OperationGeneral Call Address ACK StopNAK Stop Least Second General Call Address Second Byte DefinitionsRead n Bytes as a Slave Slave Mode Programming ExamplesInitialize Unit Write n Bytes as a SlaveWrite 1 Byte as a Master Master Programming ExamplesWrite 2 Bytes and Repeated Start Read 1 Byte as a Master Read 1 Byte as a MasterReset Conditions Read 2 Bytes as a Master Send Stop Using the AbortGlitch Suppression Logic Ibmr Bit Definitions Register Definitions1 I2C Bus Monitor Register Ibmr 2 I2C Data Buffer Register Idbr3 I2C Control Register ICR Idbr Bit Definitions10. ICR Bit Definitions Sheet 1 Beie Irfie Iteie GCD IUE 40301690 Bit ResetDisable interrupt 10. ICR Bit Definitions Sheet 2Receive mode 4 I2C Status Register ISR10. ICR Bit Definitions Sheet 3 BED SAD 11. ISR Bit Definitions Sheet 12C Status Register 40301698 BitBED SAD Gcad IRF ITE ALD SSD IBB 5 I2C Slave Address Register Isar11. ISR Bit Definitions Sheet 2 12. Isar Bit DefinitionsI2C Bus Interface Unit UARTs Feature ListCompatibility with Bluetooth UartFull Function Uart Standard UartRXD Signal DescriptionsUart Signal Descriptions Sheet 1 Name Type DescriptionUart Signal Descriptions Sheet 2 Uart Operational DescriptionLSB MSB Internal Register Descriptions ResetRBR Bit Definitions Register AccessedReceive Buffer Register RBR Uart Register Addresses as Offsets of a BaseTransmit Holding Register THR Divisor Latch Registers DLL and DLHTHR Bit Definitions Interrupt Enable Register IER DLL Bit DefinitionsDLH Bit Definitions IER Bit Definitions Interrupt Identification Register IIRFIFOES10 Interrupt ConditionsIIR Bit Definitions Sheet 1 Priority Level Interrupt origin10. Interrupt Identification Register Decode Sheet 1 Interrupt ID Bits Interrupt SET/RESET FunctionFcrresetrf IIR Bit Definitions Sheet 2ITL Fifo Control Register FCR10. Interrupt Identification Register Decode Sheet 2 11. FCR Bit Definitions Sheet 111. FCR Bit Definitions Sheet 2 Line Control Register LCR12. LCR Bit Definitions Base+0x0CUart Dlab Stkyp EPS PEN STB WLS1 WLS0 Temt Line Status Register LSR13. LSR Bit Definitions Sheet 1 FifoeTdrq 13. LSR Bit Definitions Sheet 213. LSR Bit Definitions Sheet 3 Loop OUT2 OUT1 RTS DTR Modem Control Register MCR14. MCR Bit Definitions Sheet 1 UartModem Status Register MSR 14. MCR Bit Definitions Sheet 2Base+0x10 Modem Control Register 15. MSR Bit Definitions Receive Interrupt Fifo Interrupt Mode OperationCharacter Timeout Indication Interrupt Scratchpad Register SPRFifo Polled Mode Operation DMA RequestsTransmit Interrupt Slow Infrared Asynchronous Interface Trailing Bytes in the Receive FifoInfrared Selection Register ISR 17. ISR Bit Definitions OperationIR Transmit and Receive Example Dlab Bit Name Description Uart Register Summary18. Ffuart Register Summary 19. Btuart Register Summary Sheet 120. Stuart Register Summary 19. Btuart Register Summary Sheet 2Btmsr Uart Register Differences21. Flow Control Registers in Btuart and Stuart BtmcrFicp Operation Ficp Signal DescriptionPPM Modulation Encodings 11.2.1 4PPM ModulationData Field Frame FormatAddress Field Control FieldCRC Field Baud Rate GenerationReceive Operation Transmit Operation Transmit and Receive FIFOs Ficp Register Definitions Trailing or Error Bytes in the Receive FifoICCR0 Bit Definitions Sheet 1 Ficp Control Register 0 ICCR0LBM ICCR0 Bit Definitions Sheet 2TXE TUSICCR1 Bit Definitions Ficp Control Register 1 ICCR1ICCR2 Bit Definitions Ficp Control Register 2 ICCR2Icrd Bit Definitions Ficp Data Register IcdrRFS Ficp Status Register 0 ICSR0ICSR0 Bit Definitions Sheet 1 FREICSR0 Bit Definitions Sheet 2 TUREIF ICSR1 Bit Definitions Ficp Status Register 1 ICSR1Ficp Register Summary Ficp Register SummaryUSB Overview USB Device ControllerIN/OUT Device ConfigurationEndpoint Configuration USB ProtocolBus State UDC+/UDC- Pin Levels Signalling LevelsBit Encoding USB StatesNrzi Bit Encoding Example Field FormatsStart of Frame Packet Type IN, OUT, and Setup Token Packet FormatPacket Formats Token Packet TypeBulk Transaction Type Transaction FormatsData Packet Type Handshake Packet TypeIsochronous Transaction Formats Isochronous Transaction TypeControl Transaction Type Bulk Transaction FormatsUDC Device Requests Interrupt Transaction Type10. Interrupt Transaction Formats Configuration 11. Host Device Request SummaryRequest Name UDC Hardware Connection Self-Powered DeviceWhen GPIOn and GPIOx are the Same Pin When GPIOn and GPIOx are Different PinsBus-Powered Devices UDC OperationCase 1 EP0 Control Read Case 2 EP0 Control Read with a Premature Status Stage 12-14 Intel PXA255 Processor Developer’s Manual Case 4 EP0 No Data Command Software Enables the DMACase 5 EP1 Data Transmit BULK-IN Case 6 EP2 Data Receive BULK-OUT Software Enables the EP1 InterruptSoftware Enables DMA Case 7 EP3 Data Transmit ISOCHRONOUS-INSoftware Allows the Megacell to Handle the Transaction Software Enables the EP3 Interrupt Software Enables the SOF InterruptCase 8 EP4 Data Receive ISOCHRONOUS-OUT Intel PXA255 Processor Developer’s Manual 12-19 Case 9 EP5 Data Transmit INTERRUPT-IN Case 10 Reset InterruptUDC Register Definitions Case 11 Suspend InterruptCase 12 Resume Interrupt UDC Enable UDE UDC Control Register Udccr12. Udccr Bit Definitions UDC Resume RSM Reset Interrupt Request RstirReset Interrupt Mask REM UDC Active UDA13. UDC Control Function Register ACK Control ModeACK Response Enable UDC Control Function Register Udccfr14. UDCCS0 Bit Definitions UDC Endpoint 0 Control/Status Register UDCCS0OUT Packet Ready OPR Packet Ready IPRForce Stall FST Device Remote Wakeup Feature DrwfFlush Tx Fifo FTF Sent Stall SST15. UDCCS1/6/11 Bit Definitions Setup Active SATransmit Fifo Service TFS UDC Endpoint x Control/Status Register UDCCS1/6/11Transmit Packet Complete TPC Transmit Underrun TURBit 6 Reserved UDC Endpoint x Control/Status Register UDCCS2/7/12 Transmit Short Packet TSP16. UDCCS2/7/12 Bit Definitions Bit 2 Reserved Receive Fifo Service RFSDMA Enable DME Receive Packet Complete RPCUDC Endpoint x Control/Status Register UDCCS3/8/13 Receive Short Packet RSP17. UDCCS3/8/13 Bit Definitions Bits 64 Reserved UDC Endpoint x Control/Status Register UDCCS4/9/1418. UDCCS4/9/14 Bit Definitions Receive Overflow ROFUDC Endpoint x Control/Status Register UDCCS5/10/15 Bits 54 Reserved19. UDCCS5/10/15 Bit Definitions Sheet 1 19. UDCCS5/10/15 Bit Definitions Sheet 2 UDC Interrupt Control Register 0 UICR0 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 Interrupt Mask Endpoint x IMx, Where x is 0 through20. UICR0 Bit Definitions UICR0UICR1 Interrupt Mask Endpoint x IMx, where x is 8 throughUDC Interrupt Control Register 1 UICR1 21. UICR1 Bit Definitions22. USIR0 Bit Definitions UDC Status/Interrupt Register 0 USIR0Endpoint 0 Interrupt Request IR0 Endpoint 1 Interrupt Request IR1Endpoint 5 Interrupt Request IR5 Endpoint 2 Interrupt Request IR2Endpoint 3 Interrupt Request IR3 Endpoint 4 Interrupt Request IR4Endpoint 10 Interrupt Request IR10 UDC Status/Interrupt Register 1 USIR1Endpoint 8 Interrupt Request IR8 Endpoint 9 Interrupt Request IR9UDC Frame Number High Register Ufnhr 24. Ufnhr Bit Definitions Isochronous Packet Error Endpoint 4 IPE4Isochronous Packet Error Endpoint 9 IPE9 UDC Frame Number MSB FnmsbStart of Frame Interrupt Mask SIM Isochronous Packet Error Endpoint 14 IPE14UDC Frame Number Low Register Ufnlr UDC Byte Count Register x UBCR2/4/7/9/12/14UDC Endpoint 0 Data Register UDDR0 Endpoint x Byte Count BC26. UBCR2/4/7/9/12/14 Bit Definitions 28. UDDR1/6/11 Bit Definitions UDC Endpoint x Data Register UDDR1/6/11UDC Endpoint x Data Register UDDR2/7/12 27. UDDR0 Bit Definitions30. UDDR3/8/13 Bit Definitions UDC Endpoint x Data Register UDDR3/8/13UDC Endpoint x Data Register UDDR4/9/14 29. UDDR2/7/12 Bit Definitions32. UDDR5/10/15 Bit Definitions USB Device Controller Register SummaryUDC Endpoint x Data Register UDDR5/10/15 31. UDDR4/9/14 Bit Definitions33. USB Device Controller Register Summary Sheet 2 UfnhrUfnlr 33. USB Device Controller Register Summary Sheet 3 AC’97 Controller Unit Name Direction Description summary Signal Configuration StepsExample AC-link External Interface to CODECsChannel Slots Comments AC-link Digital Serial Interface ProtocolSupported Data Stream Formats Sheet 1 SDATAIN0 SDATAIN1AC-link Audio Output Frame Sdataout Supported Data Stream Formats Sheet 2Sync AC-link Audio Output Frame Slot 1 Command Address Port Slot 0 Tag PhaseSlot 2 Bit Definitions Slot 2 Command Data PortSlot 3 PCM Playback Left Channel Slot 1 Bit DefinitionsSlots 6-11 Reserved AC-link Audio Input Frame SdatainSlot 4 PCM Playback Right Channel Slot 5 Modem Line CodecSync Slot 1 Status Address Port/SLOTREQ bits Input Slot 1 Bit Definitions Sheet 1Bit Description Slot 5 Optional Modem Line Codec Slot 2 Status Data PortSlot 3 PCM Record Left Channel Slot 4 PCM Record Right ChannelSlot 12 I/O Status AC-link Low Power ModePowering Down the AC-link Slots 7-11 ReservedWake up triggered by the Codec Waking up the AC-linkWake Up Triggered by the Acunit Cold AC’97 ResetWarm AC’97 Reset Acunit OperationInitialization 13-16 Intel PXA255 Processor Developer’s Manual Clocks and Sampling Frequencies Operational Flow for Accessing Codec RegistersTransmit Fifo Errors Receive Fifo ErrorsFIFOs Registers InterruptsGCR Bit Definitions Sheet 1 Global Control Register GCRColdrst Global Status Register GSRGCR Bit Definitions Sheet 2 WarmrstSecres Prires SCR PCR Mint Point Piint GSR Bit Definitions Sheet 1Cdone Sdone RdcsPCM-Out Control Register Pocr GSR Bit Definitions Sheet 2Pocr Bit Definitions Sheet 1 PCM-In Control Register Picr Pocr Bit Definitions Sheet 210. Picr Bit Definitions 12. Pisr Bit Definitions PCM-Out Status Register PosrPCMIn Status Register Pisr 11. Posr Bit Definitions14. Pcdr Bit Definitions Codec Access Register CARPCM Data Register Pcdr 13. CAR Bit DefinitionsMccr Register Mic-In Control Register MccrMic-In Status Register Mcsr 15. Mccr Bit DefinitionsMicindat Mic-In Data Register Mcdr16. Mcsr Bit Definitions 17. Mcdr Bit DefinitionsMocr Register Modem-Out Control Register MocrModem-In Control Register Micr 18. Mocr Bit Definitions20. Mosr Bit Definitions Modem-Out Status Register MosrModem-In Status Register Misr 19. Micr Bit DefinitionsModemdat Modem Data Register Modr21. Misr Bit Definitions 22. Modr Bit Definitions11. Modem Transmit and Receive Operation Accessing Codec Registers23. Address Mapping for Codec Registers Sheet 1 Processor Bit PhysicalAddress for a Primary Secondary Audio Codec Modem Codec 23. Address Mapping for Codec Registers Sheet 2 24. Register Mapping Summary 13.9 AC’97 Register Summary13-36 Intel PXA255 Processor Developer’s Manual Inter-Integrated-Circuit Sound I2S Controller GP29/SDATAIN GP32/SYSCLKController Operation Disabling and Enabling Audio Record Disabling and Enabling Audio ReplayTransmit Fifo Errors Receive Fifo ErrorsSerial Audio Clocks and Sampling Frequencies Sysclk = Bitclk = Fifo and Memory Format14.5.2 I2S and MSB-Justified Serial Audio Formats Supported Sampling FrequenciesI2S Data Formats 16 bits Serial Audio Controller Global Control Register SACR0 RegistersSACR0 Bit Definitions Special purpose Fifo Read/Write functionEfwr Strf Suggested Tfth and Rfth for DMA servicingFifo Write/Read table Tfth and Rfth Values for DMA ServicingDrec SACR1 Bit DefinitionsEnlbf DrplTFL Serial Audio Clock Divider Register SadivSASR0 Bit Definitions RFLSerial Audio Interrupt Clear Register Saicr Sadiv Bit DefinitionsSaicr Bit Definitions 11. Sadr Bit Descriptions Serial Audio Interrupt Mask Register SaimrSerial Audio Data Register Sadr 10. Saimr Bit Descriptions14.8 I2S Controller Register Summary Transmit and Receive Fifo Accesses Through the SadrAddress Register Description Paddr90 Name 12. Register Memory MapMultiMediaCard Controller Command Token Format MMC Data Token FormatSPI Data Token Format Mmdat MmcmdCRC MMC Controller Functional DescriptionIntel PXA255 Processor Developer’s Manual 15-5 Card Initialization Sequence Signal DescriptionMMC Controller Reset MMC Signal DescriptionMMC Mode SPI Mode Error DetectionClock Control Data FIFOs Response Data Fifo MmcresReceive Data FIFO, Mmcrxfifo Transmit Data FIFO, Mmctxfifo DMA and Program I/O Card Communication ProtocolMmcclkrt Mmcspi Mmcresto Basic, No Data, Command and Response SequenceBlock Data Write Stream Data Write Block Data ReadStream Data Read Busy SequenceStart and Stop Clock Enabling SPI ModeMultiMediaCard Controller Operation SPI FunctionalityNo Data Command and Response Sequence EraseSingle Data Block Write Single Block Read Multiple Block Read Multiple Block WriteStream Read Stream WriteMmcstrpcl Register MMC Controller RegistersStrpcl MMCStatus Register MmcstatMmcstrpcl Bit Definitions Mmcstat Bit Definitions Sheet 1Mmcstat Bit Definitions Sheet 2 Mmcclkrt Register MmcclkrtMmcspi Register Mmcspi Mmcclk Bit DefinitionsMmcspi Bit Definitions Sheet 1 Mmccmdat Register Mmccmdat Mmcspi Bit Definitions Sheet 2Mmccmdat Bit Definitions Sheet 1 Mmcresto Register Mmcresto Mmccmdat Bit Definitions Sheet 210. Mmcresto Bit Definitions Specifies the length of time before a data read time-out Mmcrdto Register Mmcrdto11. Mmcrdto Register Readto13. Mmcnob Bit Definitions Mmcblklen Register MmcblklenMmcnob Register Mmcnob 12. Mmcblklen Bit Definitions15. Mmcimask Bit Definitions Sheet 1 Mmcprtbuf Register MmcprtbufMmcimask Register Mmcimask 14. Mmcprtbuf Bit Definitions4 3 2 1 Mmcireg Register Mmcireg15. Mmcimask Bit Definitions Sheet 2 Mmcimask Register MultiMediaCard Controller16. Mmcireg Bit Definitions 17. Mmccmd Register 18. Command Index Values Sheet 1CMD Comm Mode Abbreviation Index Mmccmd Register Mmccmd18. Command Index Values Sheet 2 19. Mmcargh Bit Definitions 18. Command Index Values Sheet 3Mmcargh Register Mmcargh Mmcargl Register MmcarglResponsedata Mmcres Fifo21. MMCRES, Fifo Entry 22. MMCRXFIFO, Fifo EntryWritedata MultiMediaCard Controller Register Summary23. MMCTXFIFO, Fifo Entry 24. MMC Controller Registers Sheet 124. MMC Controller Registers Sheet 2 Network SSP Serial Port FeaturesProcessor and DMA Fifo Access SSP Serial Port I/O SignalsOperation Data Formats Trailing Bytes in the Receive Fifo16-4 Intel PXA255 Processor Developer’s Manual TI Synchronous Serial Protocol* Details SPI Protocol Details Motorola SPI* Frame Protocol multiple transfers Serial Clock Phase SPH16-8 Intel PXA255 Processor Developer’s Manual Microwire* Protocol Details PSP Details Programmable Serial Protocol multiple transfers Sspspstrtdly Programmable Serial Protocol PSP ParametersSspspscmode Sspspsfrmp11. TI SSP with SSCRTTE=1 and SSCRTTELP=0 Hi-Z on SsptxdMotorola SPI Programmable Serial Protocol 16-16 Intel PXA255 Processor Developer’s Manual Baud-Rate Generation Fifo Operation16-18 Intel PXA255 Processor Developer’s Manual FRF DSS SSCR0 Bit Definitions Sheet 1SSCR0 SCR SSEEdss DSS SSCR0 Bit Definitions Sheet 2Edss SCR SSE Data Size SelectSPH SPO LBM TIE RIE Ttelp TTE EbceiSclkdir Sfrmdir Scfr SSCR1SSP Programmable Serial Protocol Register Sspsp Sspsp Bit Definitions Sheet 1 Ssto Bit Definitions SSP Time Out Register SstoSSP Interrupt Test Register Ssitr Sspsp Bit Definitions Sheet 2Ssitr Test Receive Fifo Service Request TrfsTest Transmit Fifo Service Request Ttfs Ssitr Bit DefinitionsTint Sssr Bit Definitions Sheet 1Sssr BCE CSS TURSssr Bit Definitions Sheet 2 Receive Fifo not Empty Transmit Fifo Service RequestSssr Bit Definitions Sheet 3 SSP BusyData TRANSMIT/RECEIVE Data Network SSP Serial Port Register Summary10. Nssp Register Address Map Ssdr16-30 Intel PXA255 Processor Developer’s Manual Hardware Uart Hardware Uart Operation Uart Signal Descriptions17-4 Intel PXA255 Processor Developer’s Manual Receive Interrupt Fifo Interrupt Mode OperationFifo Polled Mode Operation Character Timeout InterruptFifo DMA Mode Operation DMA Receive Programming ErrorsDMA Error Handling Removing Trailing Bytes In DMA Mode Autoflow ControlAuto-Baud-Rate Detection 17-8 Intel PXA255 Processor Developer’s Manual Intel PXA255 Processor Developer’s Manual 17-9 Bit Reserved Byte Bits Name Description 318 Receive Buffer Register RBRTransmit Holding Register THR Divisor Latch Registers DLL and DLHDLH Interrupt Enable Register IERDivisor Latch Register High DLH Bit Definitions DLLPhysical Address Interrupt Enable Register IER 0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description NIP Interrupt Identification Register IIRIIR ABL TOD IID? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0 Priority Type Source Reset ControlInterrupt Identification Register Decode Sheet 1 0x41600008Fifo Control Register FCR Interrupt Identification Register Decode Sheet 210. FCR Bit Definitions Sheet 1 Receive Fifo Occupancy Register for 10. FCR Bit Definitions Sheet 211. for Bit Definitions ABT Auto-Baud Control Register ABRAuto-Baud Count Register ACR 12. ABR Bit DefinitionsACR Line Control Register LCR13. ACR Bit Definitions 14. LCR Bit Definitions Sheet 1Dlab Stkyp EPS PEN STB WLS Line Status Register LSR14. LCR Bit Definitions Sheet 2 Line Control Register LCR PXA255 Processor Hardware Uart15. LSR Bit Definitions Sheet 1 0x41600014 Bit? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits 0 0 0 0 Bits Name Description Modem Control Register MCR15. LSR Bit Definitions Sheet 2 Line Status Register LSR PXA255 Processor Hardware UartAFE 0x41600010 Bit Reset ? ? ? ? ? ? ? Bits16. MCR Bit Definitions Sheet 1 Physical Address Modem Control Register MCRModem Status Register MSR 16. MCR Bit Definitions Sheet 217. MSR Bit Definitions Sheet 1 18. SCR Bit Definitions Scratchpad Register SCRInfrared Selection Register ISR 17. MSR Bit Definitions Sheet 2Rxpl Txpl Xmode Rcveir Xmitir Hardware Uart Register Summary19. ISR Bit Definitions 20. Hwuart Register Locations Sheet 120. Hwuart Register Locations Sheet 2 Intel PXA255 Processor Developer’s Manual 17-27