LCD Controller

Figure 7-5. Palette Buffer Format

 

 

 

 

 

 

 

 

Individual Palette Entry

 

 

 

 

 

 

 

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Color

 

 

Red (R)

 

 

 

 

Green (G)

 

 

 

 

 

Blue (B)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Mono

 

 

 

unused

 

 

 

 

 

 

Monochrome (M)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

Base + 0x0 Base + 0x4

Little Endian Palette Entry Ordering 4-, 16- or 256-Entry Palette Buffer

31

16

15

0

 

 

 

 

 

Palette entry 1

 

Palette entry 0

 

 

 

 

 

Palette entry 3

 

Palette entry 2

 

 

 

 

Entries 4 through 255 do not exist for 1 and 2 bits/pixel.

Base + 0x1C Base + 0x20

Base + 0x1FC

Palette entry 15

Palette entry 14

 

 

Palette entry 17

Palette entry 16

 

 

Entries 16 through 255 do not exist for

 

1, 2, and 4 bits/pixel.

 

 

 

Palette entry 255

Palette entry 254

 

 

7.4.2External Frame Buffer

The external frame buffer is an off-chip memory area used to supply enough encoded pixel values to fill the entire screen one or more times. The number of pixel data values depends on the size of the screen (for example, 640 x 480 = 307,200 encoded pixel values). Figure 7-6through Figure 7-18show the memory organization within the frame buffer for each size pixel encoding.

In the following figures, “Base” refers to the initial address programmed in the FSADR register, “Palette Buffer Index” refers to the data that specifies the location in the palette buffer, and “Raw Pixel Data” refers to the actual 16-bit RGB data when the palette RAM is bypassed.

Figure 7-6. 1 Bit Per Pixel Data Memory Organization

Bit

1 bit/pixel

Bit 31 30

0

Palette Buffer Index[0]

29 28 ... 3 2 1 0

Base +

Pixel 31

Pixel 30

Pixel 29

Pixel 28

...

Pixel 3

Pixel 2

Pixel 1

Pixel 0

0x0

 

 

 

 

 

 

 

 

 

Base +

 

 

 

 

 

 

 

 

 

Pixel 63

Pixel 62

Pixel 61

Pixel 60

...

Pixel 35

Pixel 34

Pixel 33

Pixel 32

0x4

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Intel® PXA255 Processor Developer’s Manual

7-11

Page 275
Image 275
Intel PXA255 manual External Frame Buffer, Palette Buffer Format