Intel PXA255 manual Receive Fifo Service RFS, Receive Packet Complete RPC, Bit 2 Reserved

USB Device Controller

12.6.5.1Receive FIFO Service (RFS)

The receive FIFO service bit is set if the receive FIFO has one complete data packet in it and the packet has been error checked by the UDC. A complete packet may be 64 bytes, a short packet, or a zero packet. This bit is not cleared until all data has been read from both buffers.

12.6.5.2Receive Packet Complete (RPC)

The receive packet complete bit is set by the UDC when an OUT packet is received. When this bit is set, the IRx bit in the appropriate UDC status/interrupt register is set, if receive interrupts are enabled. This bit must be used to validate the other status/error bits in the endpoint(x) control/status register. Status bits are not updated until RPC is set. Status bits stay set until RPC is cleared. The exception is RNE which will get set with RPC but will clear itself once the active FIFO is empty. After clearing RPC, the next buffer will become active and the status bits will be updated accordingly, including RPC. The UDCCSx[RPC] bit is cleared by writing a 1 to it. The UDC issues NAK handshakes to all OUT tokens while this bit is set and both buffers have unread data.

12.6.5.3Bit 2 Reserved

Bit 2 is reserved for future use.

12.6.5.4DMA Enable (DME)

The dma enable is used by the UDC to control the timing of the data received interrupt. If the bit is set, the interrupt is asserted if the end of packet has been received and the receive FIFO has less than 32 bytes of data remaining in it. If the bit is not set, the interrupt is asserted when the end of packet is received and all of the received data is still in the receive FIFO.

12.6.5.5Sent Stall (SST)

The sent stall bit is set by the UDC in response to FST successfully forcing a user induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation from the host PC when a STALL handshake is returned automatically. In either event, the core does not intervene and the UDC clears the STALL status when the host sends a CLEAR_FEATURE command. Any valid data in the FIFO remains valid and the software must unload it. The endpoint operation continues normally and does not send another STALL condition, even if the UDCCSx[SST] bit is set. To allow the software to continue to send the STALL condition on the USB bus, the UDCCSx[FST] bit must be set again. The core writes a 1 to the sent stall bit to clear it.

12.6.5.6Force Stall (FST)

The core can set the force stall bit to force the UDC to issue a STALL handshake to all OUT tokens. STALL handshakes continue to be sent until the core clears this bit by sending a Clear Feature command. The UDCCSx[SST] bit is set when the STALL state is actually entered, but this may be delayed if the UDC is active when the UDCCSx[FST] bit is set. The UDCCSx[FST] bit is automatically cleared when the UDCCSx[SST] bit is set. To ensure that no data is transmitted after the Clear Feature command is sent and the host resumes IN requests, software must clear the transmit FIFO by setting the UDCCSx[FTF] bit.

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