Intel PXA255 manual Sxcnfg Bit Definitions Sheet 1, 0x4800001C

Memory Controller

Table 6-13. SXCNFG Bit Definitions (Sheet 1 of 4)

0x4800_001C SXCNFG Memory Controller

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

reserved

Reset 0

SXLATCH2

0

SXTP2		SXCA2		SXRA2		SXRL2			SXCL2			SXEN2		reserved
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

SXLATCH0

*

SXTP0	SXCA0	SXRA0	SXRL0	SXCL0	SXEN0
* *	* *	* * * * *		* * * 0 *

Bits	Name		Description
31	—	reserved
		SXMEM latching scheme for pair 2/3
		0 – Latch return data with fixed delay on MEMCLK
30	SXLATCH2	1 – Latch return data with return clock
		Must be set to a 1 to enable the return clock SDCLK for latching data. For more details on
		this return data latching, see Section 6.5.4.
		SX Memory type for partition pair 2/3
		00	– Synchronous Mask ROM (SMROM)
29:28	SXTP2	01	– reserved
		10	– non-SDRAM-like Synchronous Flash
		11 – reserved
		SX Memory column address bit count for partition pair 2/3
		00	– 7 column address bits
27:26	SXCA2	01	– 8 column address bits
		10	– 9 column address bits
		11 – 10 column address bits
		SX Memory row address bit count for partition pair 2/3
		00	– 12 row address bits
25:24	SXRA2	01	– 13 row address bits
		10	– reserved
		11 – reserved
		RAS Latency for SX Memory partition pair 2/3.
		Number of external SDCLK cycles between receiving the ACT command and the READ
		command. The unit size for SXRL2 is the external SDCLK cycle.
		IF SXTP2 = “00” (SMROM):
		000 – 1 clock
		001 – 2 clocks
23:21	SXRL2	010 – 3 clocks
		011 – 4 clocks
		100 – 5 clocks
		101 – 6 clocks
		110 – 7 clocks
		111 – 8 clocks
		IF SXTP2 = 10 (non-SDRAM timing Fast Flash), this field is not used and must be
		programmed to 111.

Intel® PXA255 Processor Developer’s Manual 6-33