I2C Bus Interface Unit

9.3.1Operational Blocks

The I2C unit is connected to the peripheral bus. The processor interrupt mechanism can be used to notify the CPU that there is activity on the I2C bus. Polling can be used instead of interrupts. The I2C unit consists of the two wire interface to the I2C bus, an 8-bit buffer for passing data to and from the processor, a set of control and status registers, and a shift register for parallel/serial conversions.

The I2C unit initiates an interrupt to the processor when a buffer is full, a buffer is empty, the I2C unit slave address is detected, arbitration is lost, or a bus error condition occurs. All interrupt conditions must be cleared explicitly by software. See Section 9.9.4 for details.

The 8-bit I2C Data Buffer Register (IDBR) is loaded with a byte of data from the shift register interface to the I2C bus when receiving data and from the processor internal bus when writing data. The serial shift register is not user accessible.

The I2C Control Register (ICR) and the I2C Status Register (ISR) are located in the I2C memory- mapped address space. The registers and their functions are defined in Section 9.9.

The I2C unit supports a fast mode operation of 400 Kbits/sec and a standard mode of 100 Kbits/sec. Refer to The I2C-Bus Specification for details.

9.3.2I2C Bus Interface Modes

The I2C unit can accomplish a transfer in different operation modes. Table 9-3summarizes the different modes.

Table 9-3. Modes of Operation

Mode

 

Description

 

 

 

• I2C unit acts as a master.

 

Used for a write operation.

Master - Transmit

I2C unit sends the data.

 

I2C unit is responsible for clocking.

 

Slave device in slave-receive mode

 

 

 

• I2C unit acts as a master.

 

Used for a read operation.

Master - Receive

I2C unit receives the data.

 

I2C unit is responsible for clocking.

 

Slave device in slave-transmit mode

 

 

 

• I2C unit acts as a slave.

Slave - Transmit

Used for a master read operation.

I2C unit sends the data.

 

 

Master device in master-receive mode.

 

 

 

• I2C unit acts as a slave.

Slave - Receive (default)

Used for a master write operation.

I2C unit receives the data.

 

 

Master device in master-transmit mode.

 

 

 

While the I2C unit is idle, it defaults to slave-receive mode. This allows the interface to monitor the bus and receive any slave addresses intended for the processor.

Intel® PXA255 Processor Developer’s Manual

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Intel PXA255 manual Operational Blocks, 2 I2C Bus Interface Modes, Modes of Operation, Mode Description