Inter-Integrated-Circuit Sound (I2S) Controller

Table 14-7. SASR0 Bit Definitions

 

 

 

Physical Address

 

 

Serial Audio Controller I2S/MSB-

 

 

 

 

 

 

 

0x4040_000C

 

 

 

 

Justified Status Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

RFL

 

 

TFL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

I2S Controller

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

reserved

ROR

TUR

RFS

TFS

BSY

RNE

TNF

 

 

 

 

 

 

 

 

 

0

0

0

0

0

0

0

0

1

 

 

 

 

 

 

 

 

 

Bits

Name

Description

 

 

 

31:16

reserved

 

 

 

15:12

RFL

Receive FIFO Level: number of entries in Receive FIFO

 

 

 

11:8

TFL

Transmit FIFO Level: number of entries in Transmit FIFO

 

 

 

7

reserved

 

 

 

 

 

Receive FIFO Overrun:

 

 

0 = Receive FIFO has not experienced an overrun

6

ROR

1 = I2S attempted data write to full Receive FIFO (Interruptible)

 

 

Can interrupt processor if bit6 of Serial Audio Interrupt Mask Register is set.

 

 

Cleared by setting bit 6 of Serial Audio Interrupt Clear Register.

 

 

 

 

 

Transmit FIFO Under-run:

 

 

0 = Transmit FIFO has not experienced an under-run

5

TUR

1 = I2S attempted data read from an empty Transmit FIFO

 

 

Can interrupt processor if bit 5 of Serial Audio Interrupt Mask Register is set.

 

 

Cleared by setting bit 5 of Serial Audio Interrupt Clear Register.

 

 

 

 

 

Receive FIFO Service Request:

 

 

0 = Receive FIFO level below RFL threshold, or I2S disabled

4

RFS

1 = Receive FIFO level is at or above RFL threshold.

 

 

Can interrupt processor if bit 4 of Serial Audio Interrupt Mask Register is set.

 

 

Cleared automatically when # of Receive FIFO entries < (RFTH + 1).

 

 

 

 

 

Transmit FIFO Service Request:

 

 

0 = Transmit FIFO level exceeds TFL threshold, or I2S disabled

3

TFS

1 = Transmit FIFO level is at or below TFL threshold

 

 

Can interrupt processor if bit 3 of Serial Audio Interrupt Mask Register is set.

 

 

Cleared automatically when # of Transmit FIFO entries >= (TFTH + 1).

 

 

 

2

BSY

I2S Busy:

0 = I2S is idle or disabled

 

 

1 = I2S currently transmitting or receiving a frame

1

RNE

Receive FIFO not empty:

0 = Receive FIFO is empty

 

 

1 = Receive FIFO is not empty

 

 

 

0

TNF

Transmit FIFO not full:

0 = Transmit FIFO is full

 

 

1 = Transmit FIFO is not full

 

 

 

14.6.4Serial Audio Clock Divider Register (SADIV)

SADIV, shown in Table 14-8, is used for generating six different BITCLK frequencies and hence six different sampling frequencies.

14-12

Intel® PXA255 Processor Developer’s Manual

Page 500
Image 500
Intel PXA255 manual Serial Audio Clock Divider Register Sadiv, SASR0 Bit Definitions, Rfl, Tfl