System Architecture

Table 2-6. Pin & Signal Descriptions for the PXA255 Processor (Sheet 6 of 9)

Pin Name

Type

Signal Descriptions

Reset State

Sleep State

 

 

 

 

 

MMCCLK/

ICOCZ

MMC clock. (output) Clock signal for the MMC

Pulled High -

Note [3]

GP[6]

Controller.

Note[1]

 

 

 

 

 

 

 

MMCCS0/

ICOCZ

MMC chip select 0. (output) Chip select 0 for the MMC

Pulled High -

Note [3]

GP[8]

Controller.

Note[1]

 

 

 

 

 

 

 

MMCCS1/

ICOCZ

MMC chip select 1. (output) Chip select 1 for the MMC

Pulled High -

Note [3]

GP[9]

Controller.

Note[1]

 

 

SSP Pins

 

 

 

 

SSPSCLK/

ICOCZ

Synchronous Serial Port Clock. (output)

Pulled High -

Note [3]

GPIO[23]

Note[1]

 

 

 

 

 

 

 

 

SSPSFRM/

ICOCZ

Synchronous Serial Port Frame. (output)

Pulled High -

Note [3]

GPIO[24]

Note[1]

 

 

 

 

 

 

 

 

SSPTXD/

ICOCZ

Synchronous Serial Port Transmit. (output)

Pulled High -

Note [3]

GPIO[25]

Note[1]

 

 

 

 

 

 

 

 

SSPRXD/

ICOCZ

Synchronous Serial Port Receive. (input)

Pulled High -

Note [3]

GPIO[26]

Note[1]

 

 

 

 

 

 

 

 

SSPEXTCLK/

ICOCZ

Synchronous Serial Port External Clock. (input)

Pulled High -

Note [3]

GPIO[27]

Note[1]

 

 

 

 

 

 

 

 

Network SSP pins

 

 

 

NSSPSCLK/

ICOCZ

Network Synchronous Serial Port Clock.

Pulled High

Note [3]

GPIO[81]

Note [1]

 

 

 

 

 

 

 

 

NSSPSFRM/

ICOCZ

Network Synchronous Serial Port Frame Signal.

Pulled High

Note [3]

GPIO[82]

Note [1]

 

 

 

 

 

 

 

 

NSSPTXD/

ICOCZ

Network Synchronous Serial Port Transmit.

Pulled High

Note [3]

GPIO[83]

Note [1]

 

 

 

 

 

 

 

 

NSSPRXD/

ICOCZ

Network Synchronous Serial Port Receive.

Pulled High

Note [3]

GPIO[84]

Note [1]

 

 

 

USB Client Pins

 

 

 

 

USB P

IAOAZ

USB Client Positive. (bidirectional)

Hi-Z

Hi-Z

 

 

 

 

 

USB N

IAOAZ

USB Client Negative pin. (bidirectional)

Hi-Z

Hi-Z

AC97 Controller

and I2S

Controller Pins

 

 

 

 

AC97 Audio Port bit clock. (input) AC97 clock is

 

 

 

 

generated by Codec 0 and fed into the PXA255

 

 

 

 

processor and Codec 1.

 

 

BITCLK/

 

AC97 Audio Port bit clock. (output) AC97 clock is

Pulled High -

 

ICOCZ

generated by the PXA255 processor.

Note [3]

GPIO[28]

Note[1]

 

I2S bit clock. (input) I2S clock is generated externally

 

 

 

 

 

 

 

and fed into PXA255 processor.

 

 

 

 

I2S bit clock. (output) I2S clock is generated by the

 

 

 

 

PXA255 processor.

 

 

 

 

 

 

 

SDATA_IN0/

ICOCZ

AC97 Audio Port data in. (input) Input line for Codec 0.

Pulled High -

Note [3]

GPIO[29]

I2S data in. (input) Input line for the I2S Controller.

Note[1]

 

 

SDATA_IN1/

 

AC97 Audio Port data in. (input) Input line for Codec 1.

Pulled High -

 

ICOCZ

I2S system clock. (output) System clock from I2S

Note [3]

GPIO[32]

Note[1]

 

Controller.

 

 

 

 

 

 

 

 

 

 

2-14

Intel® PXA255 Processor Developer’s Manual

Page 44
Image 44
Intel manual Pin & Signal Descriptions for the PXA255 Processor Sheet 6