Intel PXA255 manual ISR Bit Definitions Sheet 1, 2C Status Register, 40301698 Bit, Bed Sad

I2C Bus Interface Unit

Table 9-11. ISR Bit Definitions (Sheet 1 of 2)

Physical Address	I2C Status Register	I2C Bus Interface Unit
4030_1698

Bit	31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9
										reserved												BED	SAD
Reset	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0

8	7		6		5		4		3		2		1		0
GCAD		IRF		ITE		ALD		SSD		IBB		UB		ACKNAK		RWM
0	0		0		0		0		0		0		0		0

31:11	—	reserved
		Bus Error Detected:
		0 = No error detected.
		1 = The I2C unit sets this bit when it detects one of the following error conditions:
10	BED	• As a master transmitter, no ACK is detected on the interface after a byte is sent.
		• As a slave receiver, the I2C unit generates a NAK pulse.
		NOTE:When an error occurs, I2C bus transactions continue. Software must ensure that
		misplaced START and STOP conditions do not occur. See Section 9.4.5.
		To clear this bit, write a 1 to it.
		Slave Address Detected:
		0 = No slave address detected.
9	SAD	1 = I2C unit detected a 7-bit address that matches the general call address or ISAR. An
		interrupt is signalled when the SADIE interrupt is set to a 1.
		To clear this bit, write a 1 to it.
8	GCAD	General Call Address Detected:
		0 = No general call address received.
		1 = I2C unit received a general call address.
		IDBR Receive Full:
		0 = The IDBR has not received a new data byte or the I2C unit is idle.
7	IRF	1 = The IDBR register received a new data byte from the I2C bus. An interrupt is signalled
		when the IRFIE is set to a 1.
		To clear this bit, write a 1 to it.
		IDBR Transmit Empty:
		0 = The data byte is still being transmitted.
6	ITE	1 = The I2C unit has finished transmitting a data byte on the I2C bus. An interrupt is
		signalled when the ITEIE interrupt is set to 1.
		To clear this bit, write a 1 to it.
		Arbitration Loss Detected: used during multi-master operation.
5	ALD	0 = Cleared when arbitration is won or never took place.
		1 = Set when the I2C unit loses arbitration.
		To clear this bit, write a 1 to it.
		Slave STOP Detected:
4	SSD	0 = No STOP detected.
		1 = Set when the I2C unit detects a STOP while in slave-receive or slave-transmit mode.
		To clear this bit, write a 1 to it.
		I2C Bus Busy:
3	IBB	0 = I2C bus is idle or the I2C unit is using the bus (i.e., unit busy).
		1 = Set when the I2C bus is busy but the I2C unit is not involved in the transaction.
		Unit Busy:
2	UB	0 = I2C unit not busy.
		1 = Set when the I2C unit is busy. Defined as the time between the first START and STOP.

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