Intel PXA255 manual SSP Controller Register Summary, Receive Fifo Level RFL

Synchronous Serial Port Controller

8.7.4.8Receive FIFO Level (RFL)

This bit indicates the one less than number of entries in the Receive FIFO.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

8.8SSP Controller Register Summary

Table 8-7shows the SSP registers associated with the SSP controller and their physical addresses.

Table 8-7. SSP Controller Register Summary

Address	Abbreviation	Full Name
0x4100_0000	SSCR0	SSP Control Register 0
0x4100_0004	SSCR1	SSP Control Register 1
0x4100_0008	SSSR	SSP Status Register
0x4100_000C	—	reserved
0x4100_0010	SSDR (Write / Read)	SSP Data Write Register/SSP Data Read Register

Intel® PXA255 Processor Developer’s Manual 8-19