Intel PXA255 manual Pwm Ssp, Ost, Retains Power in Sleep, Ficp I2C MMC

Clocks and Power Manager

The clocks manager also contains clock gating for power reduction.

Figure 3-1shows a functional representation of the clocking network. “L” is in the core PLL.

The PXbus is the internal bus between the Core, the DMA/Bridge, the LCD Controller, and the Memory Controller as shown in Figure 3-1. This bus is clocked at 1/2 the run mode frequency. For optimal performance, the PXbus should be clocked as fast as possible. For example, if a target core frequency of 200 MHz is desired use 200 MHz run mode instead of 200 MHz turbo mode with run at 100 MHz. Increasing the PXbus frequency may help reduce the latency involved in accessing non-cacheable memory.

Figure 3-1. Clocks Manager Block Diagram

32.768 k		32.768 k		3.6864	3.6864	3.6864	3.6864
RTC		PWR_MGR		PWM	SSP	GPIO	OST
								CPU
				100-400				CORE
					MHz
		/1	/112		PLL*	/N
32.768				147.46				MEM
kHz
					MHz			Controller
OSC
					PLL
3.6864				95.846				/M
MHz					MHz	/4	/2
OSC					PLL		DMA
								LCD
RETAINS POWER IN SLEEP							/
								Controller
						Bridge
								PXbus
USB		FICP	I2C		MMC	UARTs	AC97	I2S
47.923	47.923		31.949		19.169	14.746	12.288	5.672

Intel® PXA255 Processor Developer’s Manual 3-3