Intel PXA255 Processor
Intel PXA255 Processor Developer’s Manual
Contents
Power Manager General Configuration Register Pcfr
Contents
Expansion Card Interface Timing Diagrams and Parameters
DMA
10-1
11-1
12.6
14.3
15.5
Figures
BitBurst-of-Eight ROM or Flash Read Timing Diagram MSC0RDF =
10-25
Tables
Clocks Manager Register Summary
Sxcnfg
10-6
10-8
12-26
15-7
Date Revision Description
Revision History
Xxiv
System Integration Features
Intel XScale Microarchitecture Features
Clocks and Power Controllers
Memory Controller
Universal Serial Bus USB Client
Inter-IC Sound I2S Controller
DMA Controller Dmac
LCD Controller
6 AC97 Controller
UARTs
Synchronous Serial Protocol Controller Sspc
Inter-Integrated Circuit I2C Bus Interface Unit
Gpio
Interrupt Control
OS Timers
Real-Time Clock RTC
Pulse-Width Modulator PWM
Introduction
Overview
System Architecture
Coprocessor 7 Register 4 Psfs Bit
Intel XScale Microarchitecture Implementation Options
Coprocessor 15 Register 0 ID Register Definition
Coprocessor 14 Register 6 and 7- Clock and Power Management
CPU Core Fault Register Bit Definitions
Coprocessor 14 Registers 0-3 Performance Monitoring
ARM ID Jtag ID
Coprocessor 15 Register 1 P-Bit
ID Bit Definitions
PXA255 Processor ID Values
I/O Ordering
Semaphores
Interrupts
ICP
Reset
Unit Sleep Mode Gpio Reset Watchdog Reset Hard Reset
USB
Selecting Peripherals vs. General Purpose I/O
Internal Registers
Processor Pin Types
Power on Reset and Boot Operation
Power Management
Pin List
Pin Name Type Signal Descriptions Reset State Sleep State
Pin & Signal Descriptions for the PXA255 Processor Sheet 1
Pin & Signal Descriptions for the PXA255 Processor Sheet 2
Psktsel
Pin & Signal Descriptions for the PXA255 Processor Sheet 3
Pin & Signal Descriptions for the PXA255 Processor Sheet 4
Pin & Signal Descriptions for the PXA255 Processor Sheet 5
Pin & Signal Descriptions for the PXA255 Processor Sheet 6
Pin & Signal Descriptions for the PXA255 Processor Sheet 7
Pwren
Pin & Signal Descriptions for the PXA255 Processor Sheet 8
Bootsel
Rtcclk Icocz
Pin Description Notes Sheet 1
Pin & Signal Descriptions for the PXA255 Processor Sheet 9
Pin Description Notes Sheet 2
Memory Map
Memory Map Part One From 0x80000000 to 0xFFFF Ffff
Memory Map Part Two From 0x00000000 to 0x7FFF Ffff
Unit Address Register Symbol Register Description
System Architecture Register Summary
System Architecture Register Address Summary Sheet 1
System Architecture Register Address Summary Sheet 2
System Architecture Register Address Summary Sheet 3
System Architecture Register Address Summary Sheet 4
Unit
System Architecture Register Address Summary Sheet 5
System Architecture Register Address Summary Sheet 6
Unit Address
System Architecture Register Address Summary Sheet 7
System Architecture Register Address Summary Sheet 8
System Architecture Register Address Summary Sheet 9
System Architecture Register Address Summary Sheet 10
System Architecture Register Address Summary Sheet 11
System Architecture Register Address Summary Sheet 12
Clock Manager Introduction
Clocks and Power Manager
Clock Manager
Power Manager Introduction
Ficp I2C MMC
Retains Power in Sleep
PWM SSP
OST
Core Phase Locked Loop
1 32.768 kHz Oscillator
2 3.6864 MHz Oscillator
Sdram
4 95.85 MHz Peripheral Phase Locked Loop
5 147.46 MHz Peripheral Phase Locked Loop
Core PLL Output Frequencies for 3.6864 MHz Crystal
Resets and Power Modes
Hardware Reset
Clock Gating
Watchdog Reset
Behavior During Gpio Reset
Gpio Reset
Completing a Watchdog Reset
Invoking Gpio Reset
Entering Turbo Mode
Run Mode
Turbo Mode
Completing Gpio Reset
Entering Idle Mode
Idle Mode
Behavior in Turbo Mode
Exiting Turbo Mode
Preparing for a Frequency Change Sequence
Behavior in Idle Mode
Exiting Idle Mode
Frequency Change Sequence
Behavior During the Frequency Change Sequence
Invoking the Frequency Change Sequence
Completing the Frequency Change Sequence
8 33-MHz Idle Mode
Behavior in 33-MHz Idle Mode
Entering 33-MHz Idle Mode
Sleep Mode
Exiting 33-MHz Idle Mode
Sleep Mode External Voltage Regulator Requirements
Entering Sleep Mode
Preparing for Sleep Mode
Clocks and Power Manager
Exiting Sleep Mode
Behavior in Sleep Mode
Clocks and Power Manager
Idle
Power Mode Summary
Power Mode Entry Sequence Table
Power Mode Exit Sequence Table Sheet 1
Power Mode Exit Sequence Table Sheet 2
Power Mode Supply Source Module Turbo Run
Power Manager Registers
Idae
Power Manager Control Register Pmcr
Pmcr Bit Definitions
Pmcr
Opde
Power Manager General Configuration Register Pcfr
Pcfr Bit Definitions
Pcfr
Pwer
Power Manager Wake-Up Enable Register Pwer
Pwer Bit Definitions
Wertc
Prer
Power Manager Rising-Edge Detect Enable Register Prer
10. Prer Bit Definitions
0x40F00010
Pfer
Power Manager Falling-Edge Detect Enable Register Pfer
11. Pfer Bit Definitions
0x40F00014
Pedr
Power Manager Gpio Edge Detect Status Register Pedr
12. Pedr Bit Definitions
0x40F00018
RDH
Power Manager Sleep Status Register Pssr
13. Pssr Bit Definitions Sheet 1
Pssr
CPU VFS
Power Manager Scratch Pad Register Pspr
13. Pssr Bit Definitions Sheet 2
14. Pspr Bit Definitions
15. Pmfw Register Bitmap and Bit Definitions
Power Manager Fast Sleep Walk-up Configuration Register Pmfw
SS9 SS8 SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0
16. PGSR0 Bit Definitions
17. PGSR1 Bit Definitions
PGSR0
PGSR2
Reset Controller Status Register Rcsr
Bit Reset 0x40F00028
18. PGSR2 Bit Definitions
Rcsr
Core Clock Configuration Register Cccr
Clocks Manager Registers
19. Rcsr Bit Definitions
Multiplier =
20. Cccr Bit Definitions
0x41300000
Bit Reserved
21. Cken Bit Definitions Sheet 1
Clock Enable Register Cken
CKEN5
Description I2S Unit Clock Enable
21. Cken Bit Definitions Sheet 2
CKEN8
Coprocessor 14 Clock and Power Management
Oscillator Configuration Register Oscc
22. Oscc Bit Definitions
Core Clock Configuration Register Cclkcfg
23. Coprocessor 14 Clock and Power Management Summary
24. Cclkcfg Bit Definitions
External Hardware Considerations
Power Mode Register Pwrmode
Power-On-Reset Considerations
Power Supply Connectivity
Clocks Manager Register Locations
Clocks and Power Manager Register Summary
Driving the Crystal Pins from an External Clock Source
Power Manager Register Summary
27. Power Manager Register Summary
Gpio Operation
General-Purpose I/O
Gpio Alternate Functions
General-Purpose I/O Block Diagram
Gpio Alternate Functions Sheet 1
Gpio Alternate Functions Sheet 2
Gpio Alternate Functions Sheet 3
MMCCS0 ALTFN1OUT
Mbgnt ALTFN1OUT
Gpio Register Definitions
Gpio Alternate Functions Sheet 4
Gpio Register Definitions Sheet 1
GPLR0
Gpio Pin-Level Registers GPLR0, GPLR1, GPLR2
Gpio Register Definitions Sheet 2
GPLR0 Bit Definitions
GPLR1
Gpio Pin Direction Registers GPDR0, GPDR1, GPDR2
GPLR1 Bit Definitions
GPLR2 Bit Definitions
GPDR0 Bit Definitions
GPDR1 Bit Definitions
GPDR2 Bit Definitions
PS9 PS8 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0
GPSR0 Bit Definitions
10. GPSR1 Bit Definitions
GPSR0
11. GPSR2 Bit Definitions
12. GPCR0 Bit Definitions
13. GPCR1 Bit Definitions
GPCR2
GPCR2 Bit Definitions
15. GRER0 Bit Definitions
16. GRER1 Bit Definitions
17. GRER2 Bit Definitions
18. GFER0 Bit Definitions
19. GFER1 Bit Definitions
GFER2 Bit Definitions
Gpio Edge Detect Status Register GEDR0, GEDR1, GEDR2
21. GEDR0 Bit Definitions
22. GEDR1 Bit Definitions
GEDR2
GEDR2 Bit Definitions
AF9 AF8 AF7 AF6 AF5 AF4 AF3 AF2 AF1 AF0
24. GAFR0L Bit Definitions
25. GAFR0U Bit Definitions
GAFR0L
GAFR1U
26. GAFR1L Bit Definitions
27. GAFR1U Bit Definitions
GAFR1L
GAFR2U
28. GAFR2L Bit Definitions
29. GAFR2U Bit Definitions
GAFR2L
Interrupt Controller Operation
Interrupt Controller
Interrupt Controller Register Definitions
Interrupt Controller Block Diagram
Icmr
Interrupt Controller Mask Register Icmr
Interrupt Controller Level Register Iclr
30. Icmr Bit Definitions
Interrupt Controller Control Register Iccr
31. Iclr Bit Definitions
32. Iccr Bit Definitions
34. Icfp Bit Definitions
33. Icip Bit Definitions
IS9 IS8
Interrupt Controller Pending Register Icpr
35. Icpr Bit Definitions Sheet 1
Icpr
IS16
Network SSP Service Request Interrupt Pending
35. Icpr Bit Definitions Sheet 2
IS14 IS13 IS12 IS11 IS10
Bit Position Source Unit
35. Icpr Bit Definitions Sheet 3
36. List of First-Level Interrupts Sheet 1
System Integration Unit
Real-Time Clock RTC
Real-Time Clock Operation
36. List of First-Level Interrupts Sheet 2
RTC Trim Register Rttr
RTC Register Definitions
RTC Alarm Register Rtar
Rttr Bit Definitions
38. Rtar Bit Definitions
Rcnr
RTC Counter Register Rcnr
RTC Status Register Rtsr
39. Rcnr Bit Definitions
Trim Procedure
Oscillator Frequency Calibration
40. Rtsr Bit Definitions
Rttr Value Calculations
Trim Example #1 Measured Value Has No Fractional Component
Trim Example #2 Measured Value Has a Fractional Component
Maximum Error Calculation Versus RTC Accuracy
Operating System OS Timer
Watchdog Timer Operation
OS Timer Register Definitions
OS Timer Match Register 0-3 OSMRx
OSMR3, OSMR2, OSMR1
OS Timer Interrupt Enable Register Oier
41. OSMRx Bit Definitions
42. Oier Bit Definitions
43. Ower Bit Definitions
OS Timer Watchdog Match Enable Register Ower
OS Timer Count Register Oscr
OS Timer Status Register Ossr
Ossr Bit Definitions
0x40A00014 Bit Reset ? ? ? ? ? ? ? ? Bits
Pulse Width Modulator
Pulse Width Modulator Operation
1.1 Interdependencies
PWMn Block Diagram
PWM Control Registers PWMCTRLn
Reset Sequence
Power Management Requirements
Register Descriptions
Prescale
PWM Duty Cycle Registers PWMDUTYn
46. PWMCTRLn Bit Definitions
0x40B00000
Fdcycle Dcycle
PWM Period Control Register PWMPERVALn
47. PWMDUTYn Bit Definitions
PWMDUTY0, PWMDUTY1
Pulse Width Modulator Output Wave Example
48. PWMPERVALn Bit Definitions
0x40B00008
System Integration Unit Register Summary
Gpio Register Locations
49. Gpio Register Addresses Sheet 1
OS Timer Register Locations
Interrupt Controller Register Locations
Real-Time Clock Register Locations
52. OS Timer Register Addresses Sheet 2
Pulse Width Modulator Register Locations
53. Pulse Width Modulator Register Addresses
DMA Description
Dmac Block Diagram
Signal Signal Type To/From Definition In/Out
Signal Descriptions
DREQ10 and PREQ370 Signals
Dmac Signal List
DMA Channel Priority Scheme
Dmairq Signal
Channel Priority
Channel Priority if all channels are running concurrently
DMA Channel Priority
No-Descriptor Fetch Mode
DMA Descriptors
Priority Schemes Examples
No-Descriptor Fetch Mode Channel State
Descriptor Fetch Mode
DMA Controller
Servicing an Interrupt
Channel States
Byte Transfer Order
Read and Write Order
Little Endian Transfers
Trailing Bytes
Servicing Internal Peripherals
Transferring Data
Dcmdincsrcaddr = Dcmdflowsrc = Dcmdflowtrg =
Drcmr
Quick Reference for DMA Programming
DMA Quick Reference for Internal Peripherals Sheet 1
Dcmd
Burst Size Source
Servicing Companion Chips and External Peripherals
DMA Quick Reference for Internal Peripherals Sheet 2
Unit Function Fifo Address Width
DMA Controller
Memory-to-Memory Moves
Dint Bit Definitions
Dmac Registers
DMA Interrupt Register Dint
DMA Channel Control/Status Register DCSRx
Stopstate Endintr Startintr Buserrintr
DCSRx Bit Definitions Sheet 1
RUN
Reqpend
DCSRx Bit Definitions Sheet 2
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chlnum
DMA Request to Channel Map Registers DRCMRx
DMA Descriptor Address Registers DDADRx
DRCMRx Bit Definitions
Stop
DMA Source Address Registers
DDADRx Bit Definitions
Descriptor Address
Srcaddr
DMA Target Address Registers DTADRx
10. DSADRx Bit Definitions
Source Address
Trgaddr
DMA Command Registers DCMDx
11. DTADRx Bit Definitions
Target Address
Size
12. DCMDx Bit Definitions Sheet 1
Incsrcaddr
Endian Width
Length
12. DCMDx Bit Definitions Sheet 2
Endian
Width
Examples
Example 1. How to set up and start a channel
Struct longddadr longdsadr longdtadr shortlength shortdcmd
13. DMA Controller Register Summary Sheet 1
DMA Controller Register Summary
13. DMA Controller Register Summary Sheet 2
13. DMA Controller Register Summary Sheet 3
13. DMA Controller Register Summary Sheet 4
13. DMA Controller Register Summary Sheet 5
Memory Controller
Sdram Interface Overview
Functional Description
Static Memory Interface / Variable Latency I/O Interface
3 16-Bit PC Card / Compact Flash Interface
Memory System Examples
Sdram Memory System Example
Static Memory System Example
Words Bits
Memory Accesses
Device Transactions
Bus Operation Burst Size
Sdram Mdcnfg Register Mdcnfg
Synchronous Dram Memory Interface
Reads and Writes
Aborts and Nonexistent Memory
Mdcnfg Bit Definitions Sheet 1
Mdcnfg Bit Definitions Sheet 2
DLATCH2
Mdcnfg Bit Definitions Sheet 3
DNB2
DADDR2
Mdmrs Bit Definitions Sheet 1
Sdram Mode Register Set Configuration Register Mdmrs
Mdmrs Bit Definitions Sheet 2
Low-Power Sdram Mode Register Set Configuration Register
Mdmrslp
Sdram Mdrefr Register Mdrefr
Mdmrslp Register Bit Definitions
0X4800
DRI
Mdrefr Bit Definitions Sheet 1
Mdrefr
APD K2DB2 K2RUN K1DB2 K1RUN E1PIN K0DB2 K0RUN E0PIN
Mdrefr Bit Definitions Sheet 2
0 1 0 0 1 * * 1
1 1 1 1 1 1 1
Fixed-Delay or Return-Clock Data Latching
Mdrefr Bit Definitions Sheet 3
APD
Number Chips Partition Size
Sdram Memory Options
Sdram Addressing Modes
Sample Sdram Memory Size Options
# Bits
‘0’
1x12x8x32 ‘0’ 1x12x8x16 1x12x9x32 1x12x9x16 1x12x10x32
Col Data
MA2410
2x13x10x16 ‘0’
Not Valid illegal addressing combination
# Bits External Address pins at Sdram RAS Time
A10
MA24 MA23
MA20
BA0
BA1 BA0
MA24
A11 A10
Memory Controller
A12
Sdram Command Overview
11. Sdram Command Encoding
12. Sdram Mode Register Opcode Table
Sdram Waveforms
Data
Sdclk
SDRAMreadsamebankdiffrow
SDCLK1 SDCKE1
SDRAMwrite
Synchronous Static Memory Interface
Synchronous Static Memory Configuration Register Sxcnfg
SXLATCH2 SXTP2 SXCA2 SXRA2 SXRL2 SXCL2 SXEN2
13. Sxcnfg Bit Definitions Sheet 1
0x4800001C
Sxcnfg
SXLATCH0
Sxcnfg Bit Definitions Sheet 2
SXLATCH2
SXRL2 SXCL2 SXEN2
13. Sxcnfg Bit Definitions Sheet 3
SXEN0
Smrom Memory Options
Sxcnfg Bit Definitions Sheet 4
SXCL0
Smrom
SXMRS2
Synchronous Static Memory Timing Diagrams
16. Sxmrs Bit Definitions
Sxmrs
Sdclk Sdcke
Non-SDRAM Timing Sxmem Operation
Memclk SDCLK0 Mdrefr
17. Read Configuration Register Programming Values
12shows the burst-of-eight read timing diagram
Non-SDRAM Timing Flash Read Timing Diagram
4.2 K3 Synchronous StrataFlash Reset
Asynchronous Static Memory
Static Memory Interface
Sram
Data Size MA0 DQM10
19 -Bit Bus Write Access
20 -Bit Bus Write Access
Data Size MA10 DQM30
21 -Bit Byte Address Bits MA10 for Reads Based on DQM30
22 -Bit Byte Address Bit MA0 for Reads Based on DQM10
23. SA-1111 Register Bit Definitions
Asynchronous Static Memory Control Registers MSCx
MSC2
24. MSC0/1/2 Bit Definitions Sheet 1
MSC0
MSC1
RRR1/3/5 RDN1/3/5 Reset RDF1/3/5
Bits Access Name
24. MSC0/1/2 Bit Definitions Sheet 2
Sram
24. MSC0/1/2 Bit Definitions Sheet 3
NWE NOE
ROM Interface
Timing Memory Clocks MSCxRTx Device
NOE
Clkmem
ROM Timing Diagrams and Parameters
RDN+1
Sram Interface Overview
Sram Timing Diagrams and Parameters
20shows the timing for Sram writes
Variable Latency I/O Vlio Interface Overview
RDF+1+Waits RRR*2+1
Variable Latency I/O Timing Diagrams and Parameters
RDF+1+Waits
Flash Memory Interface
Flash Memory Timing Diagrams and Parameters
CMD Data
23. Asynchronous 32-Bit Flash Write Timing Diagram 2 Writes
MCMEM0
Expansion Memory Timing Configuration Register
16-Bit PC Card/Compact Flash Interface
26. MCMEM0/1 Bit Definitions
MCATT1
27. MCATT0/1 Bit Definitions
28. MCIO0/1 Bit Definitions
MCATT0
MCMEMxASST XASSTHOLD XASSTWAIT +
29. Card Interface Command Assertion Code Table
CIT NOS
Expansion Memory Configuration Register Mecr
30. Mecr Bit Definition
Mecr
26 -Bit PC Card Memory Map
3 16-Bit PC Card Overview
34. Attribute Memory Space Read Commands
31. Common Memory Space Write Commands
32. Common Memory Space Read Commands
33. Attribute Memory Space Write Commands
37 -Bit I/O Space Write Commands nIOIS16 =
38 -Bit I/O Space Read Commands nIOIS16 =
External Logic for 16-Bit PC Card Implementation
DIR
Socket
29 -Bit PC Card Memory or I/O 16-Bit Half-word Access
Expansion Card Interface Timing Diagrams and Parameters
Companion Chip Interface
30 -Bit PC Card I/O 16-Bit Access to 8-Bit Device
32. Variable Latency IO
31. Alternate Bus Master Mode
Alternate Bus Master Mode
Gpio Reset
NVDDFAULT/nBATTFAULT with Pmcridae Disabled
NVDDFAULT/nBATTFAULT with Pmcridae Enabled
Bootdef Read-Only Register Bootdef
Options and Settings for Boot Memory
Alternate Booting
Boot Time Defaults
PKG Type Boot SEL
40. Bootdef Bitmap
41. Valid Boot Configurations Based on Processor Type
Bootdef
Sxcnfg
Boot-Time Configurations
34. Smrom Boot Time Configurations and Register Defaults
Memory Interface Reset and Initialization
Smrom
Mdrefr 03CA 7FFF
Hardware, Watchdog, or Sleep Reset Operation
42. Memory Controller Pin Reset Values
Pin Name PXA255 Processor Reset Value
Memory Controller
43. Memory Controller Register Summary Sheet 1
Gpio Reset Procedure
Physical Address Symbol Register Name
Memory Controller Register Summary
43. Memory Controller Register Summary Sheet 2
LCD Controller
LCD Controller
Features
LCD Controller Block Diagram
Pin Descriptions
LCD Controller Operation
Pin Descriptions
Enabling the Controller
Input FIFOs
Resetting the Controller
Detailed Module Descriptions
Disabling the Controller
Temporal Modulated Energy Distribution Tmed Dithering
Lookup Palette
Compare Range for Tmed
LCD Controller Pin Usage
Output FIFOs
Active Display Timing
Pixel Data Pins LDDx
6 DMA
Passive Display Timing
External Palette Buffer
LCD External Palette and Frame Buffers
Palette Buffer Format
External Frame Buffer
Bits Per Pixel Data Memory Organization
10 Bits Per Pixel Data Memory Organization Passive Mode
FrameBufferSize =
Functional Timing
12. Passive Mode Start-of-Frame Timing
Hsync Lbias
Vsync
Lfclk Vsync Llclk Hsync Lbias
Register Descriptions
LCD Controller Control Register 0 LCCR0
LCD Controller
LDD
LCD Controller Data Pin Utilization Sheet 1
LCD Controller Data Pin Utilization Sheet 2
Single Passive Screen Portion Pins
0x44000000 Bit Reserved
Reset X X X X X X X X X X X
LCCR0 Bit Definitions Sheet 1
LCCR0
PAS EFM IUM SFM LDM SDS CMS ENB
LCD Controller Control Register 1 LCCR1
LCCR0 Bit Definitions Sheet 2
QDM DIS DPD
LCD Controller
BLW
LCD Controller Control Register 2 LCCR2
LCCR1 Bit Definitions
BLW ELW HSW PPL
LCD Controller
BFW
LCD Controller Control Register 3 LCCR3
LCCR2 Bit Definitions
BFW EFW VSW LPP
LCD Controller
LCD Controller
DPC BPP
Reset X X X X 0 0 0
LCCR3 Bit Definitions Sheet 1
0x4400000C Bit Reserved
LCCR3 Bit Definitions Sheet 2
Reset X X X
LCD Controller DMA
Frame Descriptors
FDADR0
LCD DMA Frame Descriptor Address Registers FDADRx
LCD DMA Frame Source Address Registers FSADRx
FDADRx Bit Definitions
LCD DMA Frame ID Registers FIDRx
FSADRx Bit Definitions
FIDRx Bit Definitions
LCD DMA Command Registers LDCMDx
PAL
10. LDCMDx Bit Definitions
LDCMD0
LDCMD1
0 0 0 0 X X 0 Bits Name Description
LCD DMA Frame Branch Registers FBRx
11. FBRx Bit Definitions
Bint BRA
LCD Controller Status Register Lcsr
LCD Controller
EOF IUU IUL ABC BER SOF LDD
0x44000038 Bit Reset X X
Lcsr Bit Definitions Sheet 1
X X
Sint BS EOF QD OU IUU IUL ABC BER SOF LDD
LCD Controller Interrupt ID Register Liidr
12. Lcsr Bit Definitions Sheet 2
13. Liicr Bit Definitions
TRS
Tmed RGB Seed Register Trgbr
14. Trgbr Bit Definitions
TBS
Tmed Control Register TCR
LCD Controller Register Summary
15. TCR Bit Definitions
16. LCD Controller Register Summary Sheet 1
16. LCD Controller Register Summary Sheet 2
LCD Controller
Name Direction Description
Signal Description
External Interface to Synchronous Serial Peripherals
External Interface to Codec
Data Formats
Data Transfer
Serial Data Formats for Transfer to/from Peripherals
SSP Format Details
LSB
SPI Format Details
Sspsclk Sspsfrm
Sspsclk Sspsfrm MSB
Sspsclk Sspsfrm Ssptxd Ssprxd
Microwire Format Details
Parallel Data Formats for Fifo Storage
National Microwire* Frame Format
Baud-Rate Generation
Using Programmed I/O Data Transfers
Using DMA Data Transfers
Fifo Operation and Data Transfers
SSP Control Register 0 SSCR0
SSP Serial Port Registers
SCR
Data Size Select DSS
SSCR0 Bit Definitions
SSP Control Register 0 SSCR0
Synchronous Serial Port Enable SSE
Frame Format FRF
External Clock Select ECS
SSP Control Register 1 SSCR1
Serial Clock Rate SCR
SSCR1 Bit Definitions Sheet 1
SSCR1 Bit Definitions Sheet 2
Receive Fifo Interrupt Enable RIE
Transmit Fifo Interrupt Enable TIE
Loop Back Mode LBM
Serial Clock Phase SPH
Serial Clock Polarity SPO
Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd
Ssprxd Sspsclk SPO=0 Sspsclk SPO=1 Sspsfrm Ssptxd
Microwire Transmit Data Size Mwds
Transmit Fifo Interrupt/DMA Threshold TFT
Receive Fifo Interrupt/DMA Threshold RFT
SSP Data Register Ssdr
TFT and RFT Values for DMA Servicing
Ssdr Bit Definitions
SSP Status Register Sssr
RFL
Transmit Fifo Not Full Flag TNF
Sssr Bit Definitions
RFL TFL ROR RFS TFS BSY RNE TNF
SSP Busy Flag BSY
Transmit Fifo Service Request Flag TFS
Receive Fifo Service Request Flag RFS
Receive Fifo Not Empty Flag RNE
Address Abbreviation Full Name
SSP Controller Register Summary
Receive Fifo Level RFL
SSP Controller Register Summary
Synchronous Serial Port Controller
SCL
I2C Signal Description
Signal Name Input/Output Description
SDA
2C Device Definition
I2C Bus Definitions
Modes of Operation
Mode Description
Operational Blocks
2 I2C Bus Interface Modes
Condition
Start and Stop Bus States
Start and Stop Bit Definitions
Stop Star
Start Condition
No Start or Stop Condition
Stop Condition
ACK Stop NAK
ACK NAK
Start
ACK
I2C Bus Operation
Serial Clock Line SCL Generation
Data and Addressing Management
Addressing a Slave Device
3 I2C Acknowledge
Arbitration
Polling
SDA Arbitration
SCL Arbitration
Arbitration Procedure of Two Masters
2C Master Mode Definition Action Operation
Master Operations
Master Transactions Sheet 1
Master Transactions Sheet 2
Master-Receiver Read from Slave-Transmitter
Slave Operations
Slave Transactions
2C Slave Action Mode Definition Operation
General Call Address
ACK Stop
NAK Stop
Least Second
General Call Address Second Byte Definitions
Read n Bytes as a Slave
Slave Mode Programming Examples
Initialize Unit
Write n Bytes as a Slave
Write 1 Byte as a Master
Master Programming Examples
Write 2 Bytes and Repeated Start Read 1 Byte as a Master
Read 1 Byte as a Master
Reset Conditions
Read 2 Bytes as a Master Send Stop Using the Abort
Glitch Suppression Logic
Ibmr Bit Definitions
Register Definitions
1 I2C Bus Monitor Register Ibmr
2 I2C Data Buffer Register Idbr
3 I2C Control Register ICR
Idbr Bit Definitions
10. ICR Bit Definitions Sheet 1
Beie Irfie Iteie GCD IUE
40301690 Bit Reset
Disable interrupt
10. ICR Bit Definitions Sheet 2
Receive mode
4 I2C Status Register ISR
10. ICR Bit Definitions Sheet 3
BED SAD
11. ISR Bit Definitions Sheet 1
2C Status Register
40301698 Bit
BED SAD Gcad IRF ITE ALD SSD IBB
5 I2C Slave Address Register Isar
11. ISR Bit Definitions Sheet 2
12. Isar Bit Definitions
I2C Bus Interface Unit
UARTs
Feature List
Compatibility with
Bluetooth Uart
Full Function Uart
Standard Uart
RXD
Signal Descriptions
Uart Signal Descriptions Sheet 1
Name Type Description
Uart Signal Descriptions Sheet 2
Uart Operational Description
LSB MSB
Internal Register Descriptions
Reset
RBR Bit Definitions
Register Accessed
Receive Buffer Register RBR
Uart Register Addresses as Offsets of a Base
Transmit Holding Register THR
Divisor Latch Registers DLL and DLH
THR Bit Definitions
Interrupt Enable Register IER
DLL Bit Definitions
DLH Bit Definitions
IER Bit Definitions
Interrupt Identification Register IIR
FIFOES10
Interrupt Conditions
IIR Bit Definitions Sheet 1
Priority Level Interrupt origin
10. Interrupt Identification Register Decode Sheet 1
Interrupt ID Bits Interrupt SET/RESET Function
Fcrresetrf
IIR Bit Definitions Sheet 2
ITL
Fifo Control Register FCR
10. Interrupt Identification Register Decode Sheet 2
11. FCR Bit Definitions Sheet 1
11. FCR Bit Definitions Sheet 2
Line Control Register LCR
12. LCR Bit Definitions
Base+0x0C
Uart Dlab Stkyp EPS PEN STB WLS1 WLS0
Temt
Line Status Register LSR
13. LSR Bit Definitions Sheet 1
Fifoe
Tdrq
13. LSR Bit Definitions Sheet 2
13. LSR Bit Definitions Sheet 3
Loop OUT2 OUT1 RTS DTR
Modem Control Register MCR
14. MCR Bit Definitions Sheet 1
Uart
Modem Status Register MSR
14. MCR Bit Definitions Sheet 2
Base+0x10 Modem Control Register
15. MSR Bit Definitions
Receive Interrupt
Fifo Interrupt Mode Operation
Character Timeout Indication Interrupt
Scratchpad Register SPR
Fifo Polled Mode Operation
DMA Requests
Transmit Interrupt
Slow Infrared Asynchronous Interface
Trailing Bytes in the Receive Fifo
Infrared Selection Register ISR
17. ISR Bit Definitions
Operation
IR Transmit and Receive Example
Dlab Bit Name Description
Uart Register Summary
18. Ffuart Register Summary
19. Btuart Register Summary Sheet 1
20. Stuart Register Summary
19. Btuart Register Summary Sheet 2
Btmsr
Uart Register Differences
21. Flow Control Registers in Btuart and Stuart
Btmcr
Ficp Operation
Ficp Signal Description
PPM Modulation Encodings
11.2.1 4PPM Modulation
Data Field
Frame Format
Address Field
Control Field
CRC Field
Baud Rate Generation
Receive Operation
Transmit Operation
Transmit and Receive FIFOs
Ficp Register Definitions
Trailing or Error Bytes in the Receive Fifo
ICCR0 Bit Definitions Sheet 1
Ficp Control Register 0 ICCR0
LBM
ICCR0 Bit Definitions Sheet 2
TXE
TUS
ICCR1 Bit Definitions
Ficp Control Register 1 ICCR1
ICCR2 Bit Definitions
Ficp Control Register 2 ICCR2
Icrd Bit Definitions
Ficp Data Register Icdr
RFS
Ficp Status Register 0 ICSR0
ICSR0 Bit Definitions Sheet 1
FRE
ICSR0 Bit Definitions Sheet 2
TUR
EIF
ICSR1 Bit Definitions
Ficp Status Register 1 ICSR1
Ficp Register Summary
Ficp Register Summary
USB Overview
USB Device Controller
IN/OUT
Device Configuration
Endpoint Configuration
USB Protocol
Bus State UDC+/UDC- Pin Levels
Signalling Levels
Bit Encoding
USB States
Nrzi Bit Encoding Example
Field Formats
Start of Frame Packet Type
IN, OUT, and Setup Token Packet Format
Packet Formats
Token Packet Type
Bulk Transaction Type
Transaction Formats
Data Packet Type
Handshake Packet Type
Isochronous Transaction Formats
Isochronous Transaction Type
Control Transaction Type
Bulk Transaction Formats
UDC Device Requests
Interrupt Transaction Type
10. Interrupt Transaction Formats
Configuration
11. Host Device Request Summary
Request Name
UDC Hardware Connection
Self-Powered Device
When GPIOn and GPIOx are the Same Pin
When GPIOn and GPIOx are Different Pins
Bus-Powered Devices
UDC Operation
Case 1 EP0 Control Read
Case 2 EP0 Control Read with a Premature Status Stage
12-14 Intel PXA255 Processor Developer’s Manual
Case 4 EP0 No Data Command
Software Enables the DMA
Case 5 EP1 Data Transmit BULK-IN
Case 6 EP2 Data Receive BULK-OUT
Software Enables the EP1 Interrupt
Software Enables DMA
Case 7 EP3 Data Transmit ISOCHRONOUS-IN
Software Allows the Megacell to Handle the Transaction
Software Enables the EP3 Interrupt
Software Enables the SOF Interrupt
Case 8 EP4 Data Receive ISOCHRONOUS-OUT
Intel PXA255 Processor Developer’s Manual 12-19
Case 9 EP5 Data Transmit INTERRUPT-IN
Case 10 Reset Interrupt
UDC Register Definitions
Case 11 Suspend Interrupt
Case 12 Resume Interrupt
UDC Enable UDE
UDC Control Register Udccr
12. Udccr Bit Definitions
UDC Resume RSM
Reset Interrupt Request Rstir
Reset Interrupt Mask REM
UDC Active UDA
13. UDC Control Function Register
ACK Control Mode
ACK Response Enable
UDC Control Function Register Udccfr
14. UDCCS0 Bit Definitions
UDC Endpoint 0 Control/Status Register UDCCS0
OUT Packet Ready OPR
Packet Ready IPR
Force Stall FST
Device Remote Wakeup Feature Drwf
Flush Tx Fifo FTF
Sent Stall SST
15. UDCCS1/6/11 Bit Definitions
Setup Active SA
Transmit Fifo Service TFS
UDC Endpoint x Control/Status Register UDCCS1/6/11
Transmit Packet Complete TPC
Transmit Underrun TUR
Bit 6 Reserved
UDC Endpoint x Control/Status Register UDCCS2/7/12
Transmit Short Packet TSP
16. UDCCS2/7/12 Bit Definitions
Bit 2 Reserved
Receive Fifo Service RFS
DMA Enable DME
Receive Packet Complete RPC
UDC Endpoint x Control/Status Register UDCCS3/8/13
Receive Short Packet RSP
17. UDCCS3/8/13 Bit Definitions
Bits 64 Reserved
UDC Endpoint x Control/Status Register UDCCS4/9/14
18. UDCCS4/9/14 Bit Definitions
Receive Overflow ROF
UDC Endpoint x Control/Status Register UDCCS5/10/15
Bits 54 Reserved
19. UDCCS5/10/15 Bit Definitions Sheet 1
19. UDCCS5/10/15 Bit Definitions Sheet 2
UDC Interrupt Control Register 0 UICR0
IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0
Interrupt Mask Endpoint x IMx, Where x is 0 through
20. UICR0 Bit Definitions
UICR0
UICR1
Interrupt Mask Endpoint x IMx, where x is 8 through
UDC Interrupt Control Register 1 UICR1
21. UICR1 Bit Definitions
22. USIR0 Bit Definitions
UDC Status/Interrupt Register 0 USIR0
Endpoint 0 Interrupt Request IR0
Endpoint 1 Interrupt Request IR1
Endpoint 5 Interrupt Request IR5
Endpoint 2 Interrupt Request IR2
Endpoint 3 Interrupt Request IR3
Endpoint 4 Interrupt Request IR4
Endpoint 10 Interrupt Request IR10
UDC Status/Interrupt Register 1 USIR1
Endpoint 8 Interrupt Request IR8
Endpoint 9 Interrupt Request IR9
UDC Frame Number High Register Ufnhr
24. Ufnhr Bit Definitions
Isochronous Packet Error Endpoint 4 IPE4
Isochronous Packet Error Endpoint 9 IPE9
UDC Frame Number MSB Fnmsb
Start of Frame Interrupt Mask SIM
Isochronous Packet Error Endpoint 14 IPE14
UDC Frame Number Low Register Ufnlr
UDC Byte Count Register x UBCR2/4/7/9/12/14
UDC Endpoint 0 Data Register UDDR0
Endpoint x Byte Count BC
26. UBCR2/4/7/9/12/14 Bit Definitions
28. UDDR1/6/11 Bit Definitions
UDC Endpoint x Data Register UDDR1/6/11
UDC Endpoint x Data Register UDDR2/7/12
27. UDDR0 Bit Definitions
30. UDDR3/8/13 Bit Definitions
UDC Endpoint x Data Register UDDR3/8/13
UDC Endpoint x Data Register UDDR4/9/14
29. UDDR2/7/12 Bit Definitions
32. UDDR5/10/15 Bit Definitions
USB Device Controller Register Summary
UDC Endpoint x Data Register UDDR5/10/15
31. UDDR4/9/14 Bit Definitions
33. USB Device Controller Register Summary Sheet 2
Ufnhr
Ufnlr
33. USB Device Controller Register Summary Sheet 3
AC’97 Controller Unit
Name Direction Description summary
Signal Configuration Steps
Example AC-link
External Interface to CODECs
Channel Slots Comments
AC-link Digital Serial Interface Protocol
Supported Data Stream Formats Sheet 1
SDATAIN0 SDATAIN1
AC-link Audio Output Frame Sdataout
Supported Data Stream Formats Sheet 2
Sync
AC-link Audio Output Frame
Slot 1 Command Address Port
Slot 0 Tag Phase
Slot 2 Bit Definitions
Slot 2 Command Data Port
Slot 3 PCM Playback Left Channel
Slot 1 Bit Definitions
Slots 6-11 Reserved
AC-link Audio Input Frame Sdatain
Slot 4 PCM Playback Right Channel
Slot 5 Modem Line Codec
Sync
Slot 1 Status Address Port/SLOTREQ bits
Input Slot 1 Bit Definitions Sheet 1
Bit Description
Slot 5 Optional Modem Line Codec
Slot 2 Status Data Port
Slot 3 PCM Record Left Channel
Slot 4 PCM Record Right Channel
Slot 12 I/O Status
AC-link Low Power Mode
Powering Down the AC-link
Slots 7-11 Reserved
Wake up triggered by the Codec
Waking up the AC-link
Wake Up Triggered by the Acunit
Cold AC’97 Reset
Warm AC’97 Reset
Acunit Operation
Initialization
13-16 Intel PXA255 Processor Developer’s Manual
Clocks and Sampling Frequencies
Operational Flow for Accessing Codec Registers
Transmit Fifo Errors
Receive Fifo Errors
FIFOs
Registers
Interrupts
GCR Bit Definitions Sheet 1
Global Control Register GCR
Coldrst
Global Status Register GSR
GCR Bit Definitions Sheet 2
Warmrst
Secres Prires SCR PCR Mint Point Piint
GSR Bit Definitions Sheet 1
Cdone Sdone
Rdcs
PCM-Out Control Register Pocr
GSR Bit Definitions Sheet 2
Pocr Bit Definitions Sheet 1
PCM-In Control Register Picr
Pocr Bit Definitions Sheet 2
10. Picr Bit Definitions
12. Pisr Bit Definitions
PCM-Out Status Register Posr
PCMIn Status Register Pisr
11. Posr Bit Definitions
14. Pcdr Bit Definitions
Codec Access Register CAR
PCM Data Register Pcdr
13. CAR Bit Definitions
Mccr Register
Mic-In Control Register Mccr
Mic-In Status Register Mcsr
15. Mccr Bit Definitions
Micindat
Mic-In Data Register Mcdr
16. Mcsr Bit Definitions
17. Mcdr Bit Definitions
Mocr Register
Modem-Out Control Register Mocr
Modem-In Control Register Micr
18. Mocr Bit Definitions
20. Mosr Bit Definitions
Modem-Out Status Register Mosr
Modem-In Status Register Misr
19. Micr Bit Definitions
Modemdat
Modem Data Register Modr
21. Misr Bit Definitions
22. Modr Bit Definitions
11. Modem Transmit and Receive Operation
Accessing Codec Registers
23. Address Mapping for Codec Registers Sheet 1
Processor Bit Physical
Address for a Primary Secondary Audio Codec Modem Codec
23. Address Mapping for Codec Registers Sheet 2
24. Register Mapping Summary
13.9 AC’97 Register Summary
13-36 Intel PXA255 Processor Developer’s Manual
Inter-Integrated-Circuit Sound I2S Controller
GP29/SDATAIN
GP32/SYSCLK
Controller Operation
Disabling and Enabling Audio Record
Disabling and Enabling Audio Replay
Transmit Fifo Errors
Receive Fifo Errors
Serial Audio Clocks and Sampling Frequencies
Sysclk = Bitclk =
Fifo and Memory Format
14.5.2 I2S and MSB-Justified Serial Audio Formats
Supported Sampling Frequencies
I2S Data Formats 16 bits
Serial Audio Controller Global Control Register SACR0
Registers
SACR0 Bit Definitions
Special purpose Fifo Read/Write function
Efwr Strf
Suggested Tfth and Rfth for DMA servicing
Fifo Write/Read table
Tfth and Rfth Values for DMA Servicing
Drec
SACR1 Bit Definitions
Enlbf
Drpl
TFL
Serial Audio Clock Divider Register Sadiv
SASR0 Bit Definitions
RFL
Serial Audio Interrupt Clear Register Saicr
Sadiv Bit Definitions
Saicr Bit Definitions
11. Sadr Bit Descriptions
Serial Audio Interrupt Mask Register Saimr
Serial Audio Data Register Sadr
10. Saimr Bit Descriptions
14.8 I2S Controller Register Summary
Transmit and Receive Fifo Accesses Through the Sadr
Address Register Description Paddr90 Name
12. Register Memory Map
MultiMediaCard Controller
Command Token Format
MMC Data Token Format
SPI Data Token Format
Mmdat
Mmcmd
CRC
MMC Controller Functional Description
Intel PXA255 Processor Developer’s Manual 15-5
Card Initialization Sequence
Signal Description
MMC Controller Reset
MMC Signal Description
MMC Mode
SPI Mode
Error Detection
Clock Control
Data FIFOs
Response Data Fifo Mmcres
Receive Data FIFO, Mmcrxfifo
Transmit Data FIFO, Mmctxfifo
DMA and Program I/O
Card Communication Protocol
Mmcclkrt Mmcspi Mmcresto
Basic, No Data, Command and Response Sequence
Block Data Write
Stream Data Write
Block Data Read
Stream Data Read
Busy Sequence
Start and Stop Clock
Enabling SPI Mode
MultiMediaCard Controller Operation
SPI Functionality
No Data Command and Response Sequence
Erase
Single Data Block Write
Single Block Read
Multiple Block Read
Multiple Block Write
Stream Read
Stream Write
Mmcstrpcl Register
MMC Controller Registers
Strpcl
MMCStatus Register Mmcstat
Mmcstrpcl Bit Definitions
Mmcstat Bit Definitions Sheet 1
Mmcstat Bit Definitions Sheet 2
Mmcclkrt Register Mmcclkrt
Mmcspi Register Mmcspi
Mmcclk Bit Definitions
Mmcspi Bit Definitions Sheet 1
Mmccmdat Register Mmccmdat
Mmcspi Bit Definitions Sheet 2
Mmccmdat Bit Definitions Sheet 1
Mmcresto Register Mmcresto
Mmccmdat Bit Definitions Sheet 2
10. Mmcresto Bit Definitions
Specifies the length of time before a data read time-out
Mmcrdto Register Mmcrdto
11. Mmcrdto Register
Readto
13. Mmcnob Bit Definitions
Mmcblklen Register Mmcblklen
Mmcnob Register Mmcnob
12. Mmcblklen Bit Definitions
15. Mmcimask Bit Definitions Sheet 1
Mmcprtbuf Register Mmcprtbuf
Mmcimask Register Mmcimask
14. Mmcprtbuf Bit Definitions
4 3 2 1
Mmcireg Register Mmcireg
15. Mmcimask Bit Definitions Sheet 2
Mmcimask Register MultiMediaCard Controller
16. Mmcireg Bit Definitions
17. Mmccmd Register
18. Command Index Values Sheet 1
CMD Comm Mode Abbreviation Index
Mmccmd Register Mmccmd
18. Command Index Values Sheet 2
19. Mmcargh Bit Definitions
18. Command Index Values Sheet 3
Mmcargh Register Mmcargh
Mmcargl Register Mmcargl
Responsedata
Mmcres Fifo
21. MMCRES, Fifo Entry
22. MMCRXFIFO, Fifo Entry
Writedata
MultiMediaCard Controller Register Summary
23. MMCTXFIFO, Fifo Entry
24. MMC Controller Registers Sheet 1
24. MMC Controller Registers Sheet 2
Network SSP Serial Port
Features
Processor and DMA Fifo Access
SSP Serial Port I/O Signals
Operation
Data Formats
Trailing Bytes in the Receive Fifo
16-4 Intel PXA255 Processor Developer’s Manual
TI Synchronous Serial Protocol* Details
SPI Protocol Details
Motorola SPI* Frame Protocol multiple transfers
Serial Clock Phase SPH
16-8 Intel PXA255 Processor Developer’s Manual
Microwire* Protocol Details
PSP Details
Programmable Serial Protocol multiple transfers
Sspspstrtdly
Programmable Serial Protocol PSP Parameters
Sspspscmode
Sspspsfrmp
11. TI SSP with SSCRTTE=1 and SSCRTTELP=0
Hi-Z on Ssptxd
Motorola SPI
Programmable Serial Protocol
16-16 Intel PXA255 Processor Developer’s Manual
Baud-Rate Generation
Fifo Operation
16-18 Intel PXA255 Processor Developer’s Manual
FRF DSS
SSCR0 Bit Definitions Sheet 1
SSCR0
SCR SSE
Edss DSS
SSCR0 Bit Definitions Sheet 2
Edss SCR SSE
Data Size Select
SPH SPO LBM TIE RIE
Ttelp TTE Ebcei
Sclkdir Sfrmdir Scfr
SSCR1
SSP Programmable Serial Protocol Register Sspsp
Sspsp Bit Definitions Sheet 1
Ssto Bit Definitions
SSP Time Out Register Ssto
SSP Interrupt Test Register Ssitr
Sspsp Bit Definitions Sheet 2
Ssitr
Test Receive Fifo Service Request Trfs
Test Transmit Fifo Service Request Ttfs
Ssitr Bit Definitions
Tint
Sssr Bit Definitions Sheet 1
Sssr
BCE CSS TUR
Sssr Bit Definitions Sheet 2
Receive Fifo not Empty
Transmit Fifo Service Request
Sssr Bit Definitions Sheet 3
SSP Busy
Data TRANSMIT/RECEIVE Data
Network SSP Serial Port Register Summary
10. Nssp Register Address Map
Ssdr
16-30 Intel PXA255 Processor Developer’s Manual
Hardware Uart
Hardware Uart
Operation
Uart Signal Descriptions
17-4 Intel PXA255 Processor Developer’s Manual
Receive Interrupt
Fifo Interrupt Mode Operation
Fifo Polled Mode Operation
Character Timeout Interrupt
Fifo DMA Mode Operation
DMA Receive Programming Errors
DMA Error Handling
Removing Trailing Bytes In DMA Mode
Autoflow Control
Auto-Baud-Rate Detection
17-8 Intel PXA255 Processor Developer’s Manual
Intel PXA255 Processor Developer’s Manual 17-9
Bit Reserved Byte Bits Name Description 318
Receive Buffer Register RBR
Transmit Holding Register THR
Divisor Latch Registers DLL and DLH
DLH
Interrupt Enable Register IER
Divisor Latch Register High DLH Bit Definitions
DLL
Physical Address Interrupt Enable Register IER
0x41600004 Bit Reset ? ? ? ? ? ? ? Bits Name
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0 Description
NIP
Interrupt Identification Register IIR
IIR
ABL TOD IID
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 ? 0 0 0 0
Priority Type Source Reset Control
Interrupt Identification Register Decode Sheet 1
0x41600008
Fifo Control Register FCR
Interrupt Identification Register Decode Sheet 2
10. FCR Bit Definitions Sheet 1
Receive Fifo Occupancy Register for
10. FCR Bit Definitions Sheet 2
11. for Bit Definitions
ABT
Auto-Baud Control Register ABR
Auto-Baud Count Register ACR
12. ABR Bit Definitions
ACR
Line Control Register LCR
13. ACR Bit Definitions
14. LCR Bit Definitions Sheet 1
Dlab Stkyp EPS PEN STB WLS
Line Status Register LSR
14. LCR Bit Definitions Sheet 2
Line Control Register LCR PXA255 Processor Hardware Uart
15. LSR Bit Definitions Sheet 1
0x41600014 Bit
? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 1 1 0 0 0 0 Bits
0 0 0 0 Bits Name Description
Modem Control Register MCR
15. LSR Bit Definitions Sheet 2
Line Status Register LSR PXA255 Processor Hardware Uart
AFE
0x41600010 Bit Reset ? ? ? ? ? ? ? Bits
16. MCR Bit Definitions Sheet 1
Physical Address Modem Control Register MCR
Modem Status Register MSR
16. MCR Bit Definitions Sheet 2
17. MSR Bit Definitions Sheet 1
18. SCR Bit Definitions
Scratchpad Register SCR
Infrared Selection Register ISR
17. MSR Bit Definitions Sheet 2
Rxpl Txpl Xmode Rcveir Xmitir
Hardware Uart Register Summary
19. ISR Bit Definitions
20. Hwuart Register Locations Sheet 1
20. Hwuart Register Locations Sheet 2
Intel PXA255 Processor Developer’s Manual 17-27