UARTs

10.4.2.9Modem Control Register (MCR)

The MCR, shown in Table 10-14, uses the modem control pins nRTS and nDTR to control the interface with a modem or data set. The MCR also controls the Loopback mode. Loopback mode must be enabled before the UART is enabled. The differences between UARTs specific to this register are described in Section 10.5.1.

This is a read/write register. Ignore reads from reserved bits. Write zeros to reserved bits.

Table 10-14. MCR Bit Definitions (Sheet 1 of 2)

 

 

 

 

Base+0x10

 

 

 

 

Modem Control Register

 

 

 

 

 

 

UART

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

reserved

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read/Write

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

3

2

LOOP

 

OUT2

 

OUT1

 

 

0

0

0

1

0

RTS

 

DTR

 

 

 

 

0

0

Bits

Name

Description

 

 

 

31:5

reserved

 

 

 

 

 

Loopback Mode: This bit provides a local loopback feature for diagnostic testing of the

 

 

UART. When LOOP is set to a logic 1, the following will occur: The transmitter serial output

 

 

is set to a logic 1 state. The receiver serial input is disconnected from the pin. The output of

 

 

the Transmitter Shift register is “looped back” into the receiver shift register input. The four

 

 

modem control inputs (nCTS, nDSR, nDCD, and nRI) are disconnected from the pins and

 

 

the modem control output pins (nRTS and nDTR) are forced to their inactive state.

 

 

Coming out of the loopback mode may result in unpredictable activation of the delta bits

 

 

(bits 3:0) in the Modem Status Register. It is recommended that MSR is read once to clear

 

 

the delta bits in the MSR.

 

 

Loopback mode must be configured before the UART is enabled.

 

 

The lower four bits of the MCR are connected to the upper four Modem Status Register

4

LOOP

bits:

• DTR = 1 forces DSR to a 1

 

 

 

 

• RTS = 1 forces CTS to a 1

 

 

• OUT1 = 1 forces RI to a 1

 

 

• OUT2= 1 forces DCD to a 1

 

 

In loopback mode, data that is transmitted is immediately received. This feature allows the

 

 

processor to verify the transmit and receive data paths of the UART. The transmit, receive

 

 

and modem control interrupts are operational, except the modem control interrupts are

 

 

activated by MCR bits, not the modem control pins. A break signal can also be transferred

 

 

from the transmitter section to the receiver section in loopback mode.

 

 

0 – normal UART operation

 

 

1 – loopback mode UART operation

OUT2 signal control: OUT2 connects the UART’s interrupt output to the Interrupt Controller unit. When LOOP=0:

 

 

0 –

UART interrupt is disabled.

3

OUT2

1 –

UART interrupt is enabled.

When LOOP=1, interrupts always go to the processor:

0 – MSR[DCD] forced to a 0

1 – MSR[DCD] forced to a 1

10-18

Intel® PXA255 Processor Developer’s Manual

Page 376
Image 376
Intel PXA255 manual Modem Control Register MCR, MCR Bit Definitions Sheet 1, Uart, Loop OUT2 OUT1 RTS DTR